Design Verification Engineer

Apple•Cupertino, CA

18h•$174,149 - $225,300•Onsite

About The Position

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do. Design and implement testbench environments and test cases. Engage in regular meetings with design and micro architecture teams to comprehend the functional and performance objectives of the ongoing design projects. Thoroughly examine and assess design specifications to gain a comprehensive understanding of the project requirements. Identify potential areas for improvement or clarification. Establish a robust testbench methodology tailored to project requirements, ensuring efficient verification processes. Write Tests and Generate Test Coverage. Develop System Verilog checkers using UVM methodology to verify new debug features. Regularly update and enhance test cases to adapt to evolving project needs. Execute regular regression tests to validate the functionality and performance of the design under various scenarios. Analyze test failures, trace signals using tools like Verdi, and collaborate with the design team to address issues. Take ownership of individual tasks and deliverables, ensuring alignment with project goals and timelines.

Requirements

Writing System Verilog/Verilog RTL code to model digital circuits and digital designs.
Using System Verilog/Verilog for developing testbench code using logic design principles.
Using System Verilog/Verilog to debug RTL and testbench code.
Developing System Verilog/Verilog to develop test benches using randomized tests.
Developing UVM testbenches to verify functional correctness.
Using UVM testbenches and System Verilog/Verilog to ensure that specified design objectives such as performance, power are being met.
Utilizing Computer Architecture for SOC architecture and design.
Utilizing design verification concepts such as functional coverage metrics to verify SOC design.

Responsibilities

Design and implement testbench environments and test cases.
Engage in regular meetings with design and micro architecture teams to comprehend the functional and performance objectives of the ongoing design projects.
Thoroughly examine and assess design specifications to gain a comprehensive understanding of the project requirements.
Identify potential areas for improvement or clarification.
Establish a robust testbench methodology tailored to project requirements, ensuring efficient verification processes.
Write Tests and Generate Test Coverage.
Develop System Verilog checkers using UVM methodology to verify new debug features.
Regularly update and enhance test cases to adapt to evolving project needs.
Execute regular regression tests to validate the functionality and performance of the design under various scenarios.
Analyze test failures, trace signals using tools like Verdi, and collaborate with the design team to address issues.
Take ownership of individual tasks and deliverables, ensuring alignment with project goals and timelines.