Design Verification Engineer

Texas Instruments•Knoxville, TN

1d•Onsite

About The Position

Texas Instruments is seeking a Design Verification Engineer to join their Analog Power Products organization in Knoxville, TN. This role involves developing and executing verification strategies to ensure first-pass silicon success for next-generation analog and mixed-signal ICs used in industrial, automotive, and consumer applications. The engineer will manage the full verification cycle, including creating verification plans, building test benches, running regressions, tracking closure, and improving DV methodologies. Collaboration with analog design, digital design, and systems engineering teams is a key aspect of this position.

Requirements

Bachelor’s degree in Electrical Engineering, Electrical and Computer Engineering, Computer Engineering or related field
3+ years of experience in design verification or a related role

Nice To Haves

Experience with functional verification methodologies including simulation, assertions, and coverage-driven verification
Proficiency in SystemVerilog and UVM-based testbench development
Familiarity with RTL simulation tools (Cadence Xcelium, Synopsys VCS, or equivalent)
Experience with gate-level simulation and timing-aware verification flows
Scripting skills for regression automation and verification flow development (Python, Tcl, or Perl)
Ability to quickly ramp on new systems and processes
Ability to take the initiative and drive for results
Ability to establish strong relationships with key stakeholders critical to success, both internally and externally
Strong verbal and written communication skills
Demonstrated strong interpersonal, analytical and problem-solving skills
Ability to work in teams and collaborate effectively with people in different functions
Strong time management skills that enable on-time project delivery

Responsibilities

Developing detailed verification plans while working closely with the design and system team to ensure first pass silicon success
Developing test benches, tests and simulations at RTL and GLS
Development of SystemVerilog and Verilog-AMS behavioral models for analog circuits
Work with regression tools and develop scripts to submit cases for regression analysis
Running coverage regressions to meet the defined coverage goals
Tracking and communicating verification status, issues and concerns
Contribute to continuous improvements for quality and efficiency on DV strategy, tools, methods and flows