Design Verification Engineer

Apple•Cupertino, CA

2d•$150,400 - $225,300•Hybrid

About The Position

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do. APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Ensure bug-free first silicon for part of the SoC / IP and developing detailed test and coverage plans based on the micro-architecture. Develop verification methodology suitable for the IP, ensuring a scalable and portable environment. Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage, and developing verification plans. Execute verification plans, including design bring-up, DV environment bring- up, regression enabling all features under your care; and debugging of the test failures. Develop block, IP and Soc level test-benches track, and reporting DV progress using a variety of metrics, including bugs and coverage. Develop tests for digital and analog co-simulations. Execute Low Power simulations with Firmware and UPF. Deliver tests and sequences for ATE based electrical characterization. Participate in Post Silicon bring-up and debug. Develop testplan, tests, checkers for Firmware verification to ensure bug free Firmware delivery for the IP.

Requirements

Master’s degree or foreign equivalent in Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field
Computer architecture and VLSI design
Writing synthesizable RTL code in Verilog
Verifying a digital design
Using Python to automate design verification tasks for efficiency and increased productivity
Utilizing System Verilog to create Testbench for IP Level and System Level Verification
Participating in development and review of test plan, based on design specifications
Using C and C++ programming to model hardware behavior
Performing functional and timing simulations for verification, debug or performance analysis

Responsibilities

Ensure bug-free first silicon for part of the SoC / IP
Develop detailed test and coverage plans based on the micro-architecture
Develop verification methodology suitable for the IP, ensuring a scalable and portable environment
Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage, and developing verification plans
Execute verification plans, including design bring-up, DV environment bring- up, regression enabling all features under your care; and debugging of the test failures
Develop block, IP and Soc level test-benches track, and reporting DV progress using a variety of metrics, including bugs and coverage
Develop tests for digital and analog co-simulations
Execute Low Power simulations with Firmware and UPF
Deliver tests and sequences for ATE based electrical characterization
Participate in Post Silicon bring-up and debug
Develop testplan, tests, checkers for Firmware verification to ensure bug free Firmware delivery for the IP