Design-for-Test (DFT) Engineer — ASIC Backend – (Associate, Experienced, or Lead)
About The Position
Boeing Space, Intelligence & Weapons Systems is hiring multiple Design-for-Test (DFT) Engineers for its Boeing Electronic Products team in El Segundo, California. The team supports advanced digital subsystem development in an aerospace environment and drives architecture, verification, and post-silicon validation for leading-edge ASICs. Openings span associate, experienced, and lead levels. The role focuses on designing and validating test access mechanisms and infrastructure, including TAP/JTAG, IJTAG, boundary scan, MBIST, and scan compression. Engineers develop test artifacts and ATPG patterns, optimize coverage, validate memory tests, and support silicon debug and bring-up. The position is expected to be 100% onsite. Occasional travel and after-hours meetings may be required during critical milestones. The role is for first shift. Applicants must meet U.S. export-control requirements as a U.S. Person. The position does not require a security clearance, and the employer will not sponsor employment visas. Relocation may be available based on eligibility. Compensation depends on experience and qualifications; listed salary ranges vary by level.
Requirements
- Meet U.S. export-control compliance requirements as a U.S. Person, as defined by 22 C.F.R. § 120.15.
- Bachelor of Science degree in a listed relevant field or non-U.S. equivalent qualifications directly related to the work statement.
- At least 2 years of experience in Design for Testability (DFT) or equivalent; role level is adjustable by experience.
- Strong knowledge of ASIC/logic design flow, HDL (Verilog/SystemVerilog), static timing analysis, and ECO processes.
- Hands-on expertise with TAP/JTAG, IJTAG (IEEE 1687), boundary scan (IEEE 1149.1), MBIST, scan compression, ATPG, at-speed test, and silicon debug.
- Proficiency in scripting with Tcl, Perl, or Python and in DFT verification methodologies.
- Excellent analytical, problem-solving, and communication skills.
- Satisfy the company's Conflict of Interest assessment process.
- Work onsite at the listed location.
- Provide a cover letter or brief summary of relevant DFT experience is requested to help the application stand out.
Nice To Haves
- Experienced, Level 3: 5 or more years of related engineering experience.
- Lead, Level 4: 9 or more years of related engineering experience.
- Bachelor's or master's degree in electrical engineering, computer engineering/science, or a related field.
- Active U.S. Secret Security Clearance, or ability to obtain a U.S. Security Clearance for which U.S. citizenship is required.
- Requirements development and traceability experience.
- FPGA implementation experience, including constraints and timing closure.
- Static timing analysis experience.
- Understanding of timing fundamentals and CDC concepts.
- Verification collaboration experience.
- Experience with high-speed interfaces, processor integration, memory subsystems, or SoC integration.
- Mentoring or technical leadership exposure.
- Familiarity with industry-standard tools and methodologies.
Responsibilities
- Design and implement DFT architectures, including TAP/JTAG, IJTAG (IEEE 1687), boundary scan (BSCAN), MBIST, and scan compression.
- Develop and validate TAP/JTAG and IJTAG infrastructures, BSDL/ICL/PDL artifacts, and ATPG pattern generation.
- Drive pattern generation, coverage optimization, memory test validation, and silicon debug, including scan, at-speed testing, and bring-up.
- Integrate DFT features across the chip design flow and collaborate with cross-functional teams to ensure robust DFT integration.
- Coordinate with external partners and customers on custom DFT interfaces and security requirements when applicable.
- Contribute to the development and deployment of DFT methodologies for next-generation products.
- Attend occasional travel and after-hours meetings during critical milestones.
Benefits
- Competitive base pay and variable compensation opportunities.
- Eligible employees may enroll in health insurance, flexible spending accounts, health savings accounts, retirement savings plans, life and disability insurance programs, and programs providing paid and unpaid time away from work.
- Relocation may be offered based on candidate eligibility; basic relocation is offered for eligible internal candidates.
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What This Job Offers
Job Type
Full-time
Career Level
Entry Level
