CPU IP Design & Verification Intern – RISC-V Processor Development (Summer 2027)

GlobalFoundries•Austin, TX

7h•Onsite

About The Position

Join GlobalFoundries’ MIPS CPU IP Engineering organization for hands-on experience designing and verifying advanced RISC-V processor IP. The intern will work with CPU architects, RTL designers, and verification engineers on CPU microarchitecture, RTL implementation, functional verification, performance analysis, automation, and debug. The role is based in Austin, Texas, or Santa Clara, California. The internship program provides one-on-one mentorship, growth-focused work assignments, professional development opportunities, and opportunities to network with executives. Interns must be able to work at least 40 hours per week during the internship. The expected salary range is $20.00–$40.00; exact salary depends on qualifications, experience, and location.

Requirements

Be at least a sophomore at the time of application and actively pursuing a Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field through an accredited degree program during the internship.
Have at least a 3.0 overall GPA and be in good academic standing.
English fluency, written and verbal.
Ability to work at least 40 hours per week during the internship.
Coursework or project experience in digital logic design and computer architecture.
Familiarity with Verilog or SystemVerilog.
Understanding of CPU fundamentals, including pipelines, instruction execution, loads/stores, caches, and memory hierarchy.
Programming or scripting experience with Python, C/C++, or similar languages.
Strong analytical, problem-solving, and debugging skills.

Nice To Haves

Prior related internship or co-op experience.
Demonstrated leadership experience in the workplace, school projects, competitions, or similar settings.
Interest in leveraging AI tools and emerging technologies to enhance productivity, streamline workflows, and support decision-making.
Project management skills, including the ability to innovate, execute solutions, and navigate ambiguity.
Strong written and verbal communication skills.
Strong planning and organizational skills.
Knowledge of the RISC-V Instruction Set Architecture (ISA).
Experience with SystemVerilog/UVM, assertions, functional coverage, or constrained-random verification.
CPU architecture, microarchitecture, FPGA, ASIC, or processor-design project experience.
Familiarity with caches, memory subsystems, privilege modes, exceptions, interrupts, or virtual memory.
Experience with simulation, waveform debug, Git, and Linux.
Exposure to synthesis, lint, clock-domain crossing analysis, formal verification, or timing analysis.
Assembly-language programming experience.
Ability to work effectively in a collaborative engineering team.

Responsibilities

Support RISC-V CPU microarchitecture and SystemVerilog RTL design and development.
Contribute to CPU functions including instruction fetch and decode, execution, load/store, caches and memory interfaces, control and status registers, exceptions, and interrupts.
Develop verification tests, assertions, checkers, and functional coverage for CPU features.
Run CPU simulations and regressions and debug failures using logs, architectural traces, and waveforms.
Verify processor functionality across instructions, privilege modes, memory operations, and architectural corner cases.
Support CPU power, performance, and area analysis and optimization.
Develop Python, C/C++, or scripting-based automation to improve design, verification, regression, and debug productivity.
Document technical results and communicate findings to the engineering team.
Perform all activities safely and responsibly and support Environmental, Health, Safety & Security requirements and programs.