IP Design Verification Engineer

Intel Corporation•Santa Clara, CA
•$105,650 - $149,150•Hybrid

About The Position

As an IP Design Verification Engineer at Intel, you will help ensure the functionality, quality, and reliability of Intel designs. You will collaborate with cross-functional teams to verify complex IP blocks and contribute to product integrity and performance. The work includes developing test plans, building verification environments, and executing tests to identify and resolve issues early in the design process so that designs meet project goals. The role is part of Intel's Data Center Group, which develops solutions for computing and storage needs across enterprises, cloud providers, and communications service providers. The group focuses on next-generation technologies, workload optimization, and scalable and sustainable data center operations. This position is not eligible for Intel immigration sponsorship. It is based in Santa Clara, California, and follows a hybrid work model, with time split between the assigned Intel site and off-site work.

Requirements

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, plus at least 6 months of hands-on design verification experience through internships, academic projects, coursework, hands-on training, or relevant work; OR a Master's degree in one of these fields or a related field with no prior professional experience.
  • At least 6 months of hands-on experience with hardware description languages such as Verilog or SystemVerilog.
  • At least 6 months of hands-on experience with simulation and debugging tools such as VCS or ModelSim.
  • At least 6 months of experience with verification methodologies, including UVM.

Nice To Haves

  • Knowledge of scripting languages such as Python or Perl for automation and productivity enhancement.
  • Strong analytical and problem-solving skills to debug and resolve complex design challenges.
  • Excellent communication and collaboration abilities to thrive in cross-functional environments.

Responsibilities

  • Develop and implement detailed test plans for verification of IP blocks.
  • Build and maintain verification environments using industry-standard tools and methodologies.
  • Execute functional and performance tests to identify design issues and ensure compliance with specifications.
  • Debug and analyze failures, working with design, architecture, and validation teams to resolve complex technical challenges.
  • Generate verification reports and documentation to track progress and ensure alignment with project milestones.

Benefits

  • Competitive pay.
  • Stock bonuses.
  • Health benefits.
  • Retirement benefits.
  • Vacation.
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