IP Verification Engineer

Ericsson•Austin, TX

2d•Hybrid

About The Position

Ericsson's ASICs are the backbone of next-generation 5G networks. This role is for a Senior Design Verification Engineer within the ASIC IP organization in Austin, Texas. The team develops, tests, and delivers functional RTL blocks for critical silicon. The position involves stretching across the full verification stack and stepping into team leadership as the team scales. Responsibilities include TLM Modeling, Block- and Top-Level Verification, Testbench Architecture, HW Emulation & Acceleration, SW-Driven Verification, and Team Leadership.

Requirements

Several years of hands-on, IN INDUSTRY, RTL verification experience at block and/or top level
Strong SystemVerilog/UVM chops — not just using it, but architecting with it
Experience building testbenches from the ground up
Familiarity with technologies like SerDes, PCIe, ARM subsystems, DSPs/accelerators, or Ethernet
Scripting fluency in TCL, Python, Perl, or equivalent
Communication skills that match your technical depth
B.S. or M.S. in Electrical Engineering, Computer Engineering — or the equivalent education.

Nice To Haves

Test plan ownership — You've written test plans and directed/randomized test cases from a blank page, not inherited someone else's framework
Embedded software fluency — C and/or assembly aren't foreign languages to you; you've used them to design and test real embedded software
Deep architecture intuition — You understand how embedded CPUs, memory systems, caches, and coherency protocols actually behave under pressure — ARM-based experience is a strong plus
Protocol expertise — You've worked with AMBA interfaces (APB, AXI, ACE-Lite, CHI) and know how the bus-level details can make or break a verification strategy
Engineering toolchain comfort — Linux, GIT, LSF — you live in these environments and don't slow down because of them
Leadership instinct — You've started leading, and you're hungry to do more of it
Object-oriented thinking — You write code that others can build on, not just code that runs

Responsibilities

TLM Modeling — building transaction-level models that give the team early architectural confidence
Block- and Top-Level Verification — owning sign-off at both levels of the hierarchy
Testbench Architecture — designing and building UVM environments from a clean slate
HW Emulation & Acceleration — pushing verification beyond simulation into hardware-speed environments
SW-Driven Verification — bridging the hardware/software boundary where the hardest bugs hide
Team Leadership — mentoring engineers, influencing methodology, and helping shape how the team grows

Benefits

Choice of three medical plan options
Dental plan option
401(k) Plan with automatic 3% company contribution
Ericsson match $1 for every $1 you put into the 401(k) Plan on the first 3% of your eligible pay, plus 50 cents on every $1 on the next 2% of eligible pay (full matching contributions of 4% when contributing at least 5%)
Company-paid basic life insurance
Company-paid basic accidental death and dismemberment coverage
Company-paid short-term disability coverage
Company-paid long-term disability coverage
Option to participate in Ericsson’s Stock Purchase Plan
15 days of accrued vacation
Up to 3 personal days per year
11 annual holidays
8 hours of volunteer time
80 hours of sick time annually
Up to 16 weeks of paid maternity leave
6 weeks of parental or adoption leave at 100% of pay
Financial wellness programs
Educational assistance
Matching gifts
Recognition programs
Opportunity for an annual bonus (Short-Term Variable Compensation Plan)