Verification Engineer

Lumilens•San Jose, CA

About The Position

About Lumilens At Lumilens we are building the critical photonics infrastructure that powers tomorrow’s AI supercomputing. From chip-to-chip optical interconnects to scalable photonic engines, Lumilens is unlocking a new era of computing faster, cooler, and massively more efficient. We’re a well-funded startup backed by Mayfield and led by veterans who’ve built and scaled some of the most transformative technologies in the industry. This isn’t incremental innovation, it’s a ground-floor opportunity to rethink the optical layer from the silicon up. The market is moving fast, and we’re moving faster. You’ll work alongside a team of world-class engineers solving some of the hardest challenges in optics, systems, and scale. Every line of code, every design decision, every breakthrough you help deliver will shape the infrastructure of tomorrow. If you're looking for mission, momentum, and the chance to make an outsized impact, jump on the rocket ship. We’re just getting started. About the Role You verify the blocks and subsystems of a first-of-its-kind chiplet — building UVM testbenches, writing tests, and driving coverage to closure. Guided by the verification plan and methodology, you take assigned blocks from testbench bring-up through coverage signoff, and help debug across simulation and emulation. It’s a hands-on role with room to grow your scope as the team and the chip mature.

Requirements

BS or MS in Electrical/Computer Engineering (or equivalent experience).
3+ years of ASIC/SoC functional verification.
Solid UVM/SystemVerilog; constrained-random and coverage-driven verification.
Testbench development and coverage closure — building block/subsystem testbenches and driving functional + code coverage to closure.
Strong debug skills across simulation; scripting in Python, Perl, or TCL.
Familiarity with regression/CI flows and failure triage.

Nice To Haves

High-speed SerDes, PAM4, or FEC/coding (Reed-Solomon) verification.
UCIe, PCIe/CXL, Ethernet, or UALink VIP / compliance experience.
Mixed-signal verification (Verilog-AMS or SV real-number models).
Hardware-assisted verification — emulation (e.g., Palladium/Veloce) and/or FPGA prototyping (e.g., HAPS/Protium).
Low-power/UPF and gate-level simulation; performance-verification methodology.
Exposure to NICs, Ethernet/IB switches, or cache-coherent fabrics (multi-core / coherent fabric).
Formal verification for control/interlock logic; portable stimulus.

Responsibilities

Build and extend UVM testbenches (agents, sequences, scoreboards) for assigned blocks and subsystems.
Write directed and constrained-random tests; develop functional coverage and drive it to closure.
Verify the in-house engines against an algorithmic golden model, with programmable error injection and error-pattern coverage.
Integrate and use VIP (e.g., UCIe) and run compliance, link-training, loopback, and lane-repair scenarios.
Run regressions, triage failures, and help maintain the CI/regression flow.
Register (UVM RAL) verification, firmware co-simulation, and boot flows on the MCU subsystem.
Mixed-signal co-simulation — verifying digital blocks against behavioral / real-number models of analog/mixed-signal blocks.
Support hardware-assisted verification — bring up and run tests on emulation / FPGA prototyping.
Participate in gate-level and low-power (UPF) verification during signoff.
Collaborate with the design, architecture, modelling, and DFT teams as your blocks move through the flow.