IP Design Verification Engineer

Intel Corporation•Folsom, CA

2d•$105,650 - $149,150•Hybrid

About The Position

We are looking for a passionate FPGA/Emulation System Validation Engineer who is motivated to work on cutting-edge IPs and process nodes that power Intel products across Client, Server, and Bootable SoC Test chips, enabling Intel Foundry Customers. The experienced engineer will have an opportunity to define a robust and high-quality test coverage plan to validate various IPs and protocols on x86/ARM/RISC-V, PCIe, CXL, DDR, and UCIe using FPGA-based early prototyping and emulation validation hardware systems.

Requirements

Bachelor's degree in Electronics Engineering, Computer Engineering, or equivalent field with 3+ years of relevant work experience OR Master's degree in Electronics Engineering, Computer Engineering, or equivalent field with 1+ years of relevant work experience
Hardware experience with Verilog, VHDL, and SystemVerilog
Software experience with C, C++, and Python
Knowledge of Computer System Architecture
Hands-on experience with hardware and software debugging tools
Experience with technical specifications for architecture, microarchitecture, registers, and schematics

Nice To Haves

Experience with debug of Intel chipsets and/or CPUs
Experience with IA-Core Assembly and/or Python
Knowledge and hands-on experience with logic analyzers, oscilloscopes, and protocol analyzers
IP or full chip integration/simulation/emulation/verification experience
Familiarity with hardware tools such as VCS, Verdi, DVE, and OVM/UVM

Responsibilities

Define and develop robust, high-quality test coverage plans to validate various IPs and protocols including x86/ARM/RISC-V, PCIe, CXL, DDR, and UCIe
Scope, develop, and execute validation test plans for the latest generation IPs and SoCs
Contribute to testbench bring-up and troubleshooting involving FPGA boards, test cards, and debug tools
Deliver proper documentation for validation strategies, plans, best-known methods, and learnings
Continuously strive for innovation in problem-solving to improve test coverage, minimize project execution time, and increase efficiency
Keep validation lead and architect updated on milestone progress, challenges, risks, and impact to quality or schedule with integrity