Foundation IP Design Verification Intern (Summer 2027)
About The Position
Join GlobalFoundries’ Foundation IP team to support design verification for standard-cell libraries, memories, block-level IP, and chip-level integration across GF technologies. The internship offers hands-on experience with circuit and logic simulation, formal verification, post-silicon analysis, silicon debug, and CAD, scripting, and AI tools for VLSI design and performance prediction. Interns receive one-on-one mentorship, growth-focused work assignments, professional development opportunities, and opportunities to network with executives. The internship requires working at least 40 hours per week.
Requirements
- Be at least a sophomore at the time of application and actively pursuing a Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Science, or a related field through an accredited degree program during the internship.
- Have an overall GPA of at least 3.0 and be in good academic standing.
- English fluency, written and verbal.
- Ability to work at least 40 hours per week during the internship.
Nice To Haves
- Prior related internship or co-op experience.
- Demonstrated leadership experience in the workplace, school projects, competitions, or similar settings.
- Interest in using AI tools and emerging technologies to enhance productivity, streamline workflows, and support decision-making.
- Project management skills, including the ability to innovate and execute solutions and navigate ambiguity.
- Strong written and verbal communication skills.
- Strong planning and organizational skills.
- Coursework or project experience in VLSI design, digital logic, circuit simulation, or semiconductor devices.
- Familiarity with SPICE, Verilog, formal verification, or electronic design automation tools.
- Experience with Python, Perl, Tcl, Shell, or a similar scripting language.
- Interest in AI-assisted engineering methods, performance modeling, post-silicon analysis, or silicon debug.
Responsibilities
- Perform circuit and logic design verification using SPICE and Verilog simulation.
- Support verification of Foundation IP, including standard-cell libraries, memories, block-level IP, and chip-level integration.
- Use AI-assisted methods and engineering data to support performance prediction for Foundation IP.
- Contribute to formal verification activities and analyze verification results.
- Assist with post-silicon analysis and silicon debug for applicable Foundation IP.
- Develop scripts and use CAD tools to automate VLSI design, verification, analysis, and reporting tasks.
- Document methods, results, issues, and recommendations, and communicate findings to the engineering team.
- Perform all activities safely and responsibly and support Environmental, Health, Safety & Security requirements and programs.
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What This Job Offers
Career Level
Intern
Education Level
No Education Listed
