CPU IP Design & Verification Engineer – RISC-V (2027 New College Graduate)

GlobalFoundries • Austin, TX

2d • $86,000 - $170,000

About The Position

GlobalFoundries is seeking a new college graduate to join its MIPS CPU IP Engineering team and develop and verify advanced RISC-V processor IP. The role offers hands-on experience in CPU microarchitecture, SystemVerilog RTL implementation, functional verification, power, performance, and area analysis, automation, and debugging. The position is located in Austin, Texas, or Santa Clara, California.

The new college graduate program provides accelerated training in a fast-paced work environment, cross-functional opportunities, and talent mobility. Graduates receive mentorship, networking, and leadership opportunities.

Requirements

• Graduating with a Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a related field from an accredited degree program.
• At least a 3.0 overall GPA and proven good academic standing.
• English fluency, written and verbal.
• Strong foundation in digital logic design and computer architecture.
• Coursework, research, internship, or project experience with Verilog or SystemVerilog.
• Understanding of CPU fundamentals, including pipelines, instruction execution, loads/stores, caches, and memory hierarchy.
• Programming or scripting experience with Python, C/C++, or similar languages.
• Strong analytical, problem-solving, and debugging skills.

Nice To Haves

• Prior related internship or co-op experience.
• Demonstrated leadership experience in the workplace, school projects, competitions, or similar settings.
• Project management skills, including the ability to innovate, execute solutions, and navigate ambiguity.
• Strong written and verbal communication skills.
• Strong planning and organizational skills.
• Knowledge of the RISC-V Instruction Set Architecture (ISA).
• Experience with SystemVerilog/UVM, assertions, functional coverage, or constrained-random verification.
• CPU architecture, microarchitecture, FPGA, ASIC, or processor-design project experience.
• Familiarity with caches, memory subsystems, privilege modes, exceptions, interrupts, or virtual memory.
• Experience with simulation, waveform debugging, Git, and Linux.
• Exposure to synthesis, lint, clock-domain crossing analysis, formal verification, or timing analysis.
• Assembly-language programming experience.
• Interest in using AI-assisted engineering tools to improve RTL design, verification, automation, and debugging productivity.

Responsibilities

• Design and develop RISC-V CPU microarchitecture and SystemVerilog RTL.
• Contribute to CPU functions including instruction fetch and decode, execution, load/store, caches and memory interfaces, control and status registers, exceptions, and interrupts.
• Develop verification tests, assertions, checkers, and functional coverage for CPU features.
• Run CPU simulations and regressions and debug failures using logs, architectural traces, and waveforms.
• Support functional and coverage closure through design and verification reviews.
• Support CPU power, performance, and area analysis and optimization.
• Develop Python, C/C++, or scripting-based automation to improve design, verification, regression, and debug productivity.
• Collaborate across architecture, design, verification, performance, and implementation teams to deliver high-quality CPU IP.
• Perform activities safely and responsibly and support Environmental, Health, Safety & Security requirements and programs.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level