CPU Implementation Engineer

Apple • Cupertino, CA

3d • $184,700 - $277,600

About The Position

Apple Inc. is hiring a CPU Implementation Engineer to perform central processing unit (CPU) development in Cupertino, California, and various unanticipated locations throughout the USA. The role is responsible for top-level physical design, integration, and physical verification of Apple CPUs, including full-chip floorplanning, area optimization, block partitioning, and pin placement using industry-standard tools such as Encounter, ICC, and ICC2.

The engineer owns chip-level place and route (PnR), final CPU layout database construction and verification, and development and validation of the Power Grid, including route-ability analysis. The role also drives custom layout integration, block- and full-chip-level EM/IR, bump/RDL design, electrical verification and analysis, and formal verification. The engineer works with implementation and Computer Aided Design (CAD) teams throughout the chip design cycle to drive sign-off closure for tape-out, and with the System-on-Chip (SOC) team to meet IP technical and delivery requirements. Responsibilities also include contributing to CAD and physical design methodologies and developing chip integration and analysis flows using TCL and Python.

This position is 40 hours per week. The base pay range is $184,700–$277,600 per year, depending on skills, qualifications, experience, and location. Apple employees may be eligible for discretionary stock awards and employee stock purchase opportunities, as well as medical and dental coverage, retirement benefits, discounted products and free services, and reimbursement for certain education expenses, including tuition. The role might also be eligible for discretionary bonuses or commission payments and relocation, subject to applicable eligibility requirements and plan terms.

Requirements

• Master's degree or foreign equivalent in Electrical Engineering, Computer Engineering, or a related field.
• At least 3 years of experience in the job offered or a related occupation.
• At least 3 years of experience in full-chip place and route and top-metal-layer routing using industry-standard tools such as Synopsys ICC or ICC2.
• At least 3 years of experience using TCL or Python to automate PnR tasks, including chip layout analysis and physical design verification issues such as DRC or LVS.
• At least 3 years of experience in bump or RDL design and top-level integration as part of top-level deliverables.
• At least 3 years of experience with electrical issues involving bump or RDL design for power delivery and chip functionality.
• At least 3 years of experience using Calibre for layout verification such as LVS, DRC, or Antenna, including layout quality and fixes.
• At least 3 years of experience utilizing device physics, including device and transistor knowledge, to understand design bottlenecks.
• At least 3 years of experience in methodology development and technology-scaling impacts on design.
• At least 3 years of experience in planning and placement, with knowledge of block-level and SoC floorplans.

Responsibilities

• Perform CPU development, including top-level physical design, integration, and physical verification.
• Perform full-chip floorplanning, area optimization, block partitioning, and pin placement using industry-standard tools, including Encounter, ICC, and ICC2.
• Own chip-level place and route (PnR) and final CPU layout database construction and verification.
• Develop and validate the Power Grid, including route-ability analysis.
• Drive custom layout integration, block- and full-chip-level EM/IR, bump/RDL design, electrical verification and analysis, and formal verification.
• Work with implementation and CAD teams throughout the chip design cycle to drive sign-off closure for tape-out.
• Work with the SOC team to meet IP technical and delivery requirements.
• Participate in establishing CAD and physical design methodologies to improve area and efficiency.
• Participate in developing flows for chip integration and analysis using TCL and Python.

Benefits

• Discretionary restricted stock unit awards, subject to eligibility and plan terms.
• Opportunity to purchase Apple stock at a discount through voluntary participation in the Employee Stock Purchase Plan.
• Comprehensive medical and dental coverage.
• Retirement benefits.
• Discounted products and free services.
• Reimbursement for certain education expenses, including tuition, for formal education related to advancing an Apple career.
• Potential eligibility for discretionary bonuses or commission payments.
• Potential relocation assistance.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level