CPU Implementation Engineer

Apple • Cupertino, CA

1d

About The Position

Apple Inc. is hiring a CPU Implementation Engineer to support central processing unit development. The role performs top-level physical design, integration, and physical verification of Apple CPUs, including full-chip floorplanning, area optimization, block partitioning, and pin placement using industry-standard tools such as Encounter, ICC, and ICC2. The engineer owns chip-level place and route, final CPU layout database construction, and verification.

The position develops and validates power grids, performs routability analysis, and drives custom-layout integration, block- and full-chip-level EM/IR, bump/RDL design, electrical verification and analysis, and formal verification. The engineer works with implementation and CAD teams throughout the chip design cycle to close sign-off for tape-out, collaborates with the SoC team on IP technical and delivery requirements, and contributes to CAD and physical-design methodologies and integration and analysis flows using TCL and Python. The role is based in Cupertino, California, and various unanticipated locations throughout the USA, and is 40 hours per week.

Requirements

• Master’s degree or foreign equivalent in Electrical Engineering, Computer Engineering, or a related field.
• At least 3 years of experience in the job offered or a related occupation.
• At least 3 years of experience with full-chip place and route and top-metal-layer routing using industry-standard tools such as Synopsys ICC or ICC2.
• At least 3 years of experience using TCL or Python to automate PnR tasks, including chip-layout analysis and physical design verification issues such as DRC or LVS.
• At least 3 years of experience with bump or RDL design and top-level integration as part of top-level deliverables.
• At least 3 years of experience with electrical issues involving bump or RDL design for power delivery and chip functionality.
• At least 3 years of experience using Calibre for layout verification such as LVS, DRC, or antenna checks, including layout quality and fixes.
• At least 3 years of experience applying device physics, including device and transistor knowledge, to understand design bottlenecks.
• At least 3 years of experience in methodology development and technology-scaling impacts on design.
• At least 3 years of experience in planning and placement, with knowledge of block-level and SoC floorplanning.

Responsibilities

• Perform top-level physical design, integration, and physical verification of Apple CPUs.
• Own full-chip floorplanning, area optimization, block partitioning, and pin placement.
• Own chip-level place and route, final CPU layout database construction, and verification.
• Develop and validate power grids, including routability analysis.
• Drive custom-layout integration, block- and full-chip-level EM/IR, bump/RDL design, electrical verification and analysis, and formal verification.
• Work with implementation and CAD teams during the chip design cycle to achieve sign-off closure for tape-out.
• Work with the SoC team to meet IP technical and delivery requirements.
• Participate in establishing CAD and physical-design methodologies to improve area and efficiency.
• Participate in developing chip-integration and analysis flows using TCL and Python.

Benefits

• Comprehensive medical and dental coverage.
• Retirement benefits.
• Discounted products and free services.
• Tuition reimbursement for certain formal education related to advancing an employee’s career at Apple.
• Potential eligibility for discretionary bonuses or commission payments.
• Potential relocation assistance.
• Opportunity to participate in discretionary employee stock programs, including restricted stock unit awards and discounted Apple stock through the Employee Stock Purchase Plan.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level