Compute Subsystem Architect

International Recruiting LLC•California, CA

3d•$211,000 - $356,000

About The Position

The Compute Subsystem Architect will define and build compute subsystem capabilities ahead of product commitment. The role spans the Neoverse Compute Subsystem, including CPU core configuration, CMN topology and parameterization, cache and SLC architecture, and CHI coherency behavior. It also provides architectural guidance on chiplet and 3D-IC partitioning trade-offs, in collaboration with packaging and interconnect teams on interface definitions. The architect will shape compute subsystems for next-generation ASICs and advanced Arm computing platforms, develop performance models for many-core scaling, and assess architectural readiness against the Arm Neoverse CSS/CMN roadmap. The position owns architectural interfaces for chiplet and 3D-IC configurations, while packaging and D2D implementation are handled by dedicated teams. It offers an opportunity to influence advanced computing platform strategy and the data center CPU roadmap.

Requirements

Deep expertise in Arm CMN-series coherent mesh networks, including topology sizing, HN/SN/RN placement, SLC optimization, and QoS; Arm Neoverse CSS experience is stated as required.
Proficiency in the AMBA CHI protocol, including transaction types, snoop behavior, credit flow, and debug mechanisms.
Experience architecting for many-core scaling (32+ cores), including coherency overhead, cache/fabric co-optimization, and tail-latency analysis.
Excellent communication skills and ability to create high-quality architecture documents and present complex trade-offs to engineers and executives.
Educational background in Electrical Engineering, Computer Engineering, or Computer Science at the MS level.
Minimum 10 years of relevant industry experience.

Nice To Haves

Familiarity with CXL Type-1/2/3 and server-class RAS architecture.

Responsibilities

Architect CPU clusters, L2/L3/SLC caches, and coherent mesh fabrics for next-generation ASIC and advanced Arm computing platform products.
Recommend CMN topology, including mesh dimensions, HN-F/SN-F/RN-F placement, SLC distribution, snoop filter policy, and QoS parameters.
Build CPU subsystem performance models to assess many-core scaling, latency, bandwidth per core, and mesh congestion under AI-era workload traffic patterns.
Track the Arm Neoverse CSS/CMN roadmap, identify IP gaps, and lead technical engagement with Arm on architecture and multi-die scope.
Evaluate the impact of 3D-IC and chiplet partitioning on CMN topology, CHI credit return, and snoop timing; provide quantified constraints to packaging and physical teams and collaborate on co-design.
Align architecture with potential product landing vehicles, including custom ASIC solutions and advanced Arm platforms such as future CPU Dielet configurations.
Prepare architecture specifications and technical documents, and present trade-offs to engineering leadership and executives.
Own architectural interfaces for chiplet and 3D-IC configurations; packaging and D2D implementation are handled by dedicated teams.