ATE Test Engineer

NVIDIA•Santa Clara, CA

9d•$132,000 - $253,000

About The Position

This Test Engineer position supports NVIDIA’s Integrated Circuit Defect Analysis (FA) team. The engineer enables tailored test equipment and software for the Advantest PS5000 and Teradyne UltraFLEXPlus platforms, works closely with the product test engineering team, and is embedded in the FA team. The role bridges design, automated test equipment (ATE), and IC failure analysis by co-developing specialized test equipment, adapting FA methodologies, and creating test scripts for diagnostics and root-cause isolation on advanced, high-performance silicon. The position includes porting and developing test vectors, patterns, and software; converting design simulation data into test patterns; collaborating on electrical test flows that reproduce physical FA steps; optimizing tester performance and diagnostic software; and designing, prototyping, and validating custom hardware for FA setups.

Requirements

B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related technical field, or equivalent experience.
At least 5 years of hands-on experience with Advantest V93000 (PS5000) in the SmarTEST 8 environment and Teradyne UltraFLEXPlus using IG-XL software.
Proficiency with script automation using Python, C++, or Perl, and digital vector processing and debugging.
Familiarity with IC failure-analysis flows, failure isolation, electrical fault localization, and yield analysis.

Responsibilities

Port and develop test vectors, patterns, and software on the Advantest V93000 system, specifically the PS5000 module, and Teradyne UltraFLEXPlus platforms.
Convert design simulation data, such as VCD, EVCD, and STIL, into functional, scan, and structural test patterns to recreate IC failures on the tester.
Work with FA engineers, design teams, and test floor technicians to translate physical FA steps, such as ATE-assisted EMMI or OBIRCH, into reproducible electrical test flows.
Improve turnaround time from device failure to root cause by optimizing tester hardware bandwidth, signal integrity, and diagnostic software flows.
Design, prototype, and validate custom test hardware, such as specialized load boards, probe cards, and device-under-test (DUT) interfaces, for FA setups.