ASIC/RTL Design Engineer for High-speed Interfaces

Qualcomm•San Diego, CA

7d•$140,000 - $210,000

About The Position

The Mixed-Signal IP team at Qualcomm is seeking skilled micro architect and digital design engineers to contribute to the development of next-generation, high-performance, low-power interface IPs - including SerDes, DDR, and die-to-die interconnects - for integration across Qualcomm’s product portfolio, including mobile, compute, data center, and AI. In this role, you will collaborate with a cross-functional team to architect, design, implement, and validate complex IP blocks. Your work will directly support multiple business units and require a strong grasp of the full ASIC design flow, from RTL through GDSII, along with an understanding of the challenges associated with advanced semiconductor technologies.

Requirements

Master’s degree in Electrical Engineering, Computer Engineering, or a related field
7+ years of experience in RTL and ASIC design
5+ years of hands-on experience in micro-architecture and digital design for mixed-signal IPs such as SerDes (PCIe, USB, UFS, MIPI), DDR PHY, PLLs, DACs, ADCs, and sensors
Proficiency with industry-standard front-end ASIC design tools including VCS, Fusion Compiler, PrimeTime, Power Compiler (PTPX), DFT Compiler, Spyglass, and others

Nice To Haves

Ph.D. in Electrical Engineering with 5+ years of industry experience in high-speed digital circuit design
Strong background in low-power digital design techniques
Expertise in computer architecture, digital signal processing, and algorithm development
Experience developing automation scripts and design productivity tools using Python or Perl

Responsibilities

Architect and define the digital design of high-speed interface IPs (e.g., SerDes, DDR, die-to-die) in close collaboration with system architecture and analog design teams
Develop micro-architecture and implement RTL for complex mixed-signal IP blocks
Apply advanced techniques in computer architecture, digital signal processing, and ASIC design to enhance power, performance, and area (PPA)
Utilize industry-standard ASIC design tools for lint checking, clock domain crossing (CDC) analysis, design-for-test (DFT), synthesis, formal verification (FV), and static timing analysis (STA)
Design and analyze DFT logic, including ATPG for stuck-at fault (SAF) and transition delay fault (TDF) coverage
Create comprehensive design documentation, including hardware specifications
Collaborate with the design verification (DV) team to define test plan, verify the design, and fix bugs
Work with the physical design (PD) team to support floorplanning, placement, and timing closure of IPs
Support SoC integration and debug, including pre-silicon simulation and post-silicon bring-up