ASIC Power Engineer, ML Accelerators
About The Position
As an ASIC Power Engineer on Google’s TPU power design team, you will help improve the power efficiency of Tensor Processing Units (TPUs) that accelerate AI/ML workloads in data centers. You will develop power models, drive convergence to power goals, and propose and implement power optimization techniques. The role calls for a background in modeling and optimizing chip power, along with an understanding of system-level power considerations and tradeoffs. As an ASIC Design Engineer, you will contribute to project definition, design, architecture, documentation, and implementation of next-generation data center accelerators. You will collaborate with software and system teams on power management architectures and help develop custom silicon for Google’s AI and infrastructure systems.
Requirements
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 8 years of experience in silicon design or architecture, such as logic design, power architecture, performance, or SoC design.
- Experience with power design, power modeling, power architecture, or power reduction methodologies and techniques.
Nice To Haves
- Master’s degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
- Experience defining and implementing chip-wide power management architectures and designs.
- Experience in power modeling, measurement, and correlation across pre- and post-silicon phases.
- Understanding of modern power and thermal management techniques at both silicon and system levels, including DVFS, turboing, thermal management, and system-level tradeoffs.
- Ability to solve open-ended power and performance problems under ambiguity.
Responsibilities
- Contribute to design power modeling and drive convergence to power goals.
- Investigate, specify, and deploy architectural and microarchitectural power optimization techniques.
- Define best practices and methodologies to achieve low-power designs.
- Collaborate with cross-functional software and system teams to create novel power management architectures to meet power goals.
Benefits
- 15% bonus target
- Equity
- Benefits
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What This Job Offers
Job Type
Full-time
Career Level
Senior
