ASIC Power Manager, ML Accelerators
About The Position
As a Power Design Manager within Google's silicon team, you will provide technical leadership to a group of power design engineers focused on ASIC power architecture, design, and project execution. You will own complex technical projects from concept and planning through execution and closure, and guide your team in delivering designs that work correctly the first time with optimal power. The role focuses on large SoC power architecture and design for TPU technology supporting Google's AI/ML applications. You will work with IP and chip vendors and manufacturers, and across organizational boundaries to coordinate technical input and execution for SoC-centric products used in Google's computing infrastructure. The broader AI and Infrastructure team develops AI and infrastructure capabilities at scale for Google users, Google Cloud customers, and Googlers.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 10 years of experience with ASIC or SoC design.
- Experience with power design, power modeling, power architecture, or power reduction methodologies and techniques.
Nice To Haves
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
- 5 years of experience managing mid-sized ASIC/SoC design teams focused on power design and optimization.
- Experience defining and implementing chip-wide power management architectures and designs.
- Experience in power modeling, measurement, and correlation across pre-silicon and post-silicon phases.
- Understanding of modern power and thermal management techniques at the silicon and system levels, including DVFS, turboing, thermal management, and system-level tradeoffs.
- Ability to solve open-ended power and performance problems under ambiguity.
Responsibilities
- Manage a power design team responsible for power architecture, power optimization, and system power integration.
- Lead an experienced team and define processes, methods, and tools to continuously improve the power efficiency of TPU designs.
- Contribute to design power modeling and drive convergence to power targets.
- Investigate, specify, and deploy architectural and microarchitectural power optimization techniques, defining best practices and methodologies for low-power RTL designs.
- Collaborate with cross-functional software and system teams to create power management architectures that meet power goals.
- Own and drive complex technical projects from concept and planning through execution and closure.
- Work with IP and chip vendors and manufacturers, and coordinate technical input and execution across organizational boundaries.
Benefits
- 20% bonus target
- Equity
- Benefits
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What This Job Offers
Job Type
Full-time
Career Level
Manager
