ASIC & FPGA Design Engineer Stf

Lockheed Martin•Orlando, FL

20h•Remote

About The Position

The ASIC & FPGA Design Engineer will be part of the ASIC/FPGA department at Lockheed Martin Missiles and Fire Control. This team specializes in delivering full custom analog and mixed signal ICs for advanced defense systems, covering process nodes from 130 nm down to 12 nm, including high voltage BCD processes. The role involves owning the entire layout flow, from floorplan to tape out, collaborating with circuit designers to create high-performance, parasitic-aware physical designs. The engineer will work in a dual tool environment (Synopsys Custom Compiler and Cadence Virtuoso) and manage physical verification closure across multiple foundries, supporting mission-critical programs.

Requirements

Associate degree or higher in Electrical Engineering, Electronics Technology, Microelectronics, or a related technical discipline
8 or more years of experience in full-custom analog or mixed-signal IC layout design
Layout experience across process nodes ranging from 130nm to 12nm, including BCD technologies
Proficiency with Synopsys Custom Compiler (or Custom Designer)
Proficiency with Cadence Virtuoso layout environment
Experience with physical verification closure (DRC, LVS, ERC, ANT) across multiple foundry processes
Ability to obtain a U.S. security clearance
MUST BE A U.S. CITIZEN

Nice To Haves

Bachelor degree or higher in Electrical Engineering, Microelectronics, or a related field
EMIR analysis experience, including IR drop and electromigration mitigation
Scripting or layout automation skills (SKILL, Tcl, Python, or Perl)
Layout experience with precision analog blocks such as PLLs, ADC/DACs, LDOs, bandgap references, or amplifiers

Responsibilities

Create floorplans, place and route analog blocks, optimizing area, matching, signal integrity and power delivery.
Drive DRC, LVS and ERC verification to achieve full closure for each target process.
Perform or support EMIR analysis to detect and remediate IR drop and electromigration concerns.
Develop and maintain layout methodology, automation scripts and best practice guidelines for the department.
Collaborate with circuit designers, verification engineers and system architects to ensure the layout reflects functional intent and performance targets.
Manage tape out sign off packages, including documentation, design rule decks and release notes.
Mentor junior layout engineers and promote an inclusive, knowledge sharing culture.