ASIC Engineering Technical Leader - Emulation

Cisco•San Jose, CA

9d•Onsite

About The Position

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

Requirements

Bachelor's degree with 10+ years of related experience, or Master's degree with 7+ years of related experience, or Ph.D. with 5+ years of related experience.
Strong experience with SystemVerilog, UVM, and modern verification methodologies, including hardware emulation.
Experience developing and executing verification strategies for complex ASIC or SoC programs.
Experience leading verification teams or serving as the technical lead for complex verification projects.
Proficiency in scripting languages such as Python or Perl

Nice To Haves

Experience with Datacenter, Hyperscaler, AI, or networking ASICs.
Deep understanding of high-speed protocols (e.g., PCIe, Ethernet, CXL, HBM, DDR) and large-scale SoC architectures.
Hands-on experience with hardware emulation platforms such as FPGA prototyping, Cadence Palladium, Siemens Veloce/StratoCS, or Synopsys ZeBu.
Experience with silicon bring-up, post-silicon validation, and debug.
Experience optimizing verification productivity, regression infrastructure, and automation.
Strong technical leadership, communication, collaboration, and mentoring skills

Responsibilities

Lead the planning and execution of ASIC verification for complex networking SoCs, ensuring high-quality and predictable project execution.
Drive verification strategy, testplan development, coverage closure, and execution across multiple IPs and subsystem-level verification efforts.
Provide technical leadership and mentorship to verification engineers, promoting best practices and technical excellence.
Develop and enhance scalable, reusable verification environments, infrastructure, and methodologies using SystemVerilog/UVM.
Collaborate closely with architecture, RTL, emulation, FPGA, and post-silicon teams to enable efficient debug and successful silicon bring-up.
Lead complex debug efforts, perform root cause analysis, and drive issues to closure across simulation, emulation, and silicon.
Champion continuous improvements in verification productivity, automation, regression efficiency, and quality metrics.
Evaluate and adopt new verification technologies, methodologies, and industry best practices to improve verification effectiveness.

Benefits

medical, dental and vision insurance
a 401(k) plan with a Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
grants of Cisco restricted stock units
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation time per full calendar year (non-exempt employees)
flexible vacation time off program (exempt employees)
80 hours of sick time off provided on hire date and each January 1st thereafter
up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer
annual bonuses (for non-sales roles)
performance-based incentive pay (for sales roles)