ASIC Technical Leader - Product Quality & Productization (Hybrid)

Cisco•San Jose, CA

1d•$214,100 - $309,800•Hybrid

About The Position

This position provides high-level technical leadership for the Silicon One organization, bridging the gap between advanced DFT architecture, silicon quality, and high-volume manufacturing. The role is responsible for the end-to-end product lifecycle—from RTL design and NPI through mass production—ensuring that our programmable silicon architecture maintains the highest industry standards for reliability, yield, and field performance.

Requirements

20+ years in Silicon DFT, Test, Quality, and Program Management; minimum of 5 years specifically within high-reliability hardware environments.
Deep knowledge of the full ASIC development lifecycle, specifically within the Silicon One pipeline and advanced FinFET processes (6nm/7nm).
Mastery of Synopses suite (Design Compiler, Tetramax, Spyglass, VCS) and ATE (93K testers).
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related technical field.

Nice To Haves

Data Analytics: Validated expertise in Statistical Process Control (SPC) and diagnostic tools (JMP, Python, SQL).
Leadership: Proven success in leading multidisciplinary teams, influencing high-stakes technical partnerships, and translating complex data into actionable executive insights.

Responsibilities

Direct the development and execution of robust DFT architectures (JTAG, SCAN, BIST) and integrate test modes at the top-level RTL.
Guide multi-functional teams in integrating Design-for-Manufacturability (DFM) and DFT principles early in the development cycle to ensure optimal test coverage.
Orchestrate the transition of complex SoC products from development through New Product Introduction (NPI) to successful mass production.
Manage program risks and provide executive-level status reporting on manufacturing health and yield optimization.
Lead high-level Root Cause Analysis (RCA) initiatives, using advanced diagnostics to drive corrective and preventative actions.
Supervise comprehensive product qualification, including Environmental Stress Screening (ESS), electrical characterization, and accelerated life testing.
Implement advanced yield analysis, power binning, and fuse array repairs to drive DPPM to industry-leading lows.
Monitor high-volume manufacturing data to identify trends, optimize process windows, and drive continuous yield improvement.
Ensure adherence to global quality standards (ISO 9001) and maintain comprehensive technical documentation for all quality plans.

Benefits

medical, dental and vision insurance
a 401(k) plan with a Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
grants of Cisco restricted stock units
10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees (non-exempt)
flexible vacation time off program (exempt)
80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer
annual bonuses (for non-sales roles)
performance-based incentive pay (for sales roles)