ASIC Engineer

Cisco•San Jose, CA

About The Position

Cisco Silicon One develops complex, high-performance silicon ASICs used in networks, data centers, and service-provider and enterprise platforms. The ASIC Engineer will own the front-end design of ASIC subsystems from end to end and contribute to a multidisciplinary engineering team responsible for meeting product power, performance, and area goals. The role involves designing and implementing high-frequency, high-performance RTL in Verilog/SystemVerilog, helping define development processes and tools, and solving challenging problems in high-performance silicon for hyperscale infrastructure. The engineer will lead design specifications and technical reviews, influence system architecture and key subsystem design decisions, and coordinate technical execution across architecture, design, verification, and physical implementation teams. The role also includes collaboration on functional coverage, timing closure, and integration challenges; reusable-code development; mentoring engineers; and debugging and root-cause analysis from simulation through system bring-up and post-silicon validation.

Requirements

Bachelor's degree in Electrical or Computer Engineering and 7+ years of ASIC design experience, or a Master's degree in Electrical or Computer Engineering and 4+ years of ASIC design experience.
ASIC design experience delivering silicon from microarchitecture, specification, and RTL coding through tape-out, including multiple ASIC tape-outs at advanced technology nodes.
Experience in high-performance RTL design using Verilog/SystemVerilog.
Understanding of timing closure, power optimization, and clock-gating techniques.
Experience with ASIC development flows, including simulation, synthesis, and static timing analysis.

Nice To Haves

Experience in documentation, problem-solving, and technical communication.
Experience working cross-functionally and collaborating with technical teams.
Self-starter who is highly motivated and enjoys tackling new challenges and innovative technology.
Enjoyment of working in a dynamic team environment and an out-of-the-box approach to problem-solving.

Responsibilities

Define, design, and own the front-end development of ASIC subsystems for Cisco platforms.
Contribute to meeting product power, performance, and area goals within a multidisciplinary engineering team.
Help define processes, methods, and tools for complex design and implementation work.
Design and implement high-frequency, high-performance RTL in Verilog/SystemVerilog to meet timing, power, and area targets.
Lead design specifications and technical reviews, ensuring architectural clarity and high-quality implementation.
Drive technical execution across architecture, design, verification, and physical implementation teams.
Collaborate with verification and physical design teams to address functional coverage, timing, and integration challenges.
Mentor engineers and improve engineering rigor, design quality, and technical execution.
Lead debug and root-cause analysis across simulation, system bring-up, and post-silicon validation.
Create reusable code that promotes efficiency.
Influence system architecture and key design decisions across complex ASIC subsystems.

Benefits

Medical insurance
Dental insurance
Vision insurance
401(k) plan with Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Paid holidays
Floating holiday for non-exempt employees
Paid birthday day off
Paid year-end holiday shutdown
Personal wellness days
Vacation time or flexible vacation time off, depending on employee classification
Sick time off
Additional paid time away may be requested for critical or emergency family issues
Optional paid volunteer days
Annual bonuses for non-sales roles, subject to Cisco policies
Potential grants of Cisco restricted stock units, subject to eligibility and continued employment