ASIC Design Verification Eng II Full Time - United States
About The Position
This posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens. Applications accepted until further notice. Meet the Team The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world. Your Impact As an ASIC Engineer, you will play a critical role in developing Cisco’s revolutionary data center solutions. You will collaborate closely with verification engineers, designers, hardware, and other cross-functional teams to verify the ASIC in simulation, in emulation, and during ASIC bring-up to help guarantee seamless integration and optimal performance of Cisco’s hardware platforms.
Requirements
- Meet one of the following (completed within the past 3 years or expected to be completed within the next 12 months): -A Master's degree with 0 years of work experience; -A Bachelor's degree with 2 years of work experience.
- Qualifying education and work experience should be in ASIC Engineering, Verification or a related field.
- Experience with System Verilog and UVM methodology.
- Experience with scripting using Perl and/or Python.
Nice To Haves
- Experience using UVM and SystemVerilog for ASIC verification and verifying complex blocks and/or clusters within ASICs.
- Experience with functional coverage and constrained random DV environments.
- Experience in verifying complex blocks, clusters and top level for SoC.
- Experience with Veloce/HAPS.
- Experience building test benches from scratch, including experience in SystemVerilog constraints, structures, and classes.
- Effective verbal and written communication skills.
Responsibilities
- Maintaining existing DV environments and enhancing them
- Construct test bench including scoreboard, agents, sequencers, and monitors for new blocks
- Write test plan, develop test cases, debug regression failures and drive to module verification closure
- Ensuring complete verification coverage through implementation and review of code and functional coverage.
Benefits
- medical, dental and vision insurance
- a 401(k) plan with a Cisco matching contribution
- paid parental leave
- short and long-term disability coverage
- basic life insurance
- grants of Cisco restricted stock units
- 10 paid holidays per full calendar year
- 1 floating holiday for non-exempt employees
- 1 paid day off for employee’s birthday
- paid year-end holiday shutdown
- 4 paid days off for personal wellness
- 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees (non-exempt)
- flexible vacation time off program (exempt)
- 80 hours of sick time off provided on hire date and each January 1st thereafter
- up to 80 hours of unused sick time carried forward from one calendar year to the next
- Additional paid time away may be requested to deal with critical or emergency issues for family members
- Optional 10 paid days per full calendar year to volunteer
- annual bonuses (for non-sales roles)
- performance-based incentive pay (for sales roles)
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
