ASIC DFT Engineer II Full Time - United States
About The Position
You will be in the Silicon One development organization as an ASIC Design for Test Engineer with a primary focus on Design-for-Test. You will work with frontend RTL teams, backend Physical Design teams to understand chip architecture and drive DFT requirements early in the design cycle. You will implement the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug, and diagnostics needs of the designs. You will create and enhance automation scripts to improve implementation robustness and efficiency. You will work closely with the Design, Design Verification, and Physical Design teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows. You will collaborate with team members to validate test timing and logic equivalency of designs using SystemVerilog. You will utilize ATPG and EDA tools (TestMax, Tetramax, Tessent, PrimeTime) for test pattern generation and analysis.
Requirements
- A Master's degree with 0 years of work experience; or A Bachelor's degree with 2 years of work experience.
- Qualifying education and work experience should be in ASIC Engineering or a related field.
- Foundational understanding or academic/internship exposure to JTAG protocols, scan architectures, and BIST (Built-In Self-Test, including memory BIST and boundary scan).
- Familiarity or introductory hands-on exposure to EDA and ATPG tools along with scripting or coding skills in Python, Tcl, or Perl.
- Experience working with gate-level simulations and debugging using simulators like VCS.
Nice To Haves
- Practical experience or strong coursework in verification skills, including SystemVerilog, logic equivalency checking, and test-timing validation.
- Understanding of basic VLSI circuit physical behaviors in silicon (such as electromigration and temperature/voltage variation effects) and familiarity with basic timing concepts (setup/hold times, metastability).
- Exposure to post-silicon validation using DFT patterns and Test Static Timing Analysis.
- Strong verbal and written communication skills to collaborate effectively with frontend RTL, backend physical design, and verification teams.
Responsibilities
- Implement the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug, and diagnostics needs of the designs.
- Create and enhance automation scripts to improve implementation robustness and efficiency.
- Work closely with the Design, Design Verification, and Physical Design teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
- Collaborate with team members to validate test timing and logic equivalency of designs using SystemVerilog.
- Utilize ATPG and EDA tools (TestMax, Tetramax, Tessent, PrimeTime) for test pattern generation and analysis.
Benefits
- medical, dental and vision insurance
- a 401(k) plan with a Cisco matching contribution
- paid parental leave
- short and long-term disability coverage
- basic life insurance
- grants of Cisco restricted stock units
- 10 paid holidays per full calendar year
- 1 floating holiday for non-exempt employees
- 1 paid day off for employee’s birthday
- paid year-end holiday shutdown
- 4 paid days off for personal wellness
- 16 days of paid vacation time per full calendar year (non-exempt employees)
- flexible vacation time off program (exempt employees)
- 80 hours of sick time off provided on hire date and each January 1st thereafter
- up to 80 hours of unused sick time carried forward from one calendar year to the next
- optional 10 paid days per full calendar year to volunteer
- annual bonuses (for non-sales roles)
- performance-based incentive pay (for sales roles)
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
