ASIC Design Engineer (eInfochips)
About The Position
eInfochips, an Arrow company (Fortune #154), is a leading global provider of product engineering and semiconductor design services. With a rich history of over two decades, eInfochips has developed over 500+ products and achieved 40 million deployments in 140 countries, continuing to drive technological innovation across multiple verticals. eInfochips collaborates with strategic technology partners including Qualcomm, NVIDIA, NXP, Analog Devices, Texas Instruments, Amazon, Microsoft, and Google. Supported by Arrow's $38 billion in revenue, 22,000 employees, and 345 locations serving over 80 countries, eInfochips is positioned to accelerate connected product innovation for over 150,000 global clients. eInfochips serves as a catalyst for Arrow’s Sensor-to-Sunset initiative, providing comprehensive edge-to-cloud capabilities to its clients. Visit www.einfochips.com to explore their portfolio of product engineering services across various industries and verticals.
Requirements
- Proficient in Verilog/System Verilog coding constructs.
- Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting).
- Experience with high speed PCIe designs and protocols.
- Experience with Industry standard interface protocols such as AXI, APB, etc.
- Experience with ARM Fabric IPs.
- Experience with IPXACT.
- Understanding of Computer Architecture fundamentals.
- Ability to write scripts using Python, Tcl, Perl etc.
- Experience in EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus.
- Proficiency with UPF (Low power intent).
- Proficiency in clock crossing techniques.
- Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals.
- Good in understanding RTL Design and Digital concepts.
- Strong experience with EDA tools: Fusion Compiler, CDC.
- Scripting: Pearl, Python, TCL.
- At least 5+ years of experience in Verilog Design.
- AMBA AXI bus along-with ARM or C based processor.
Nice To Haves
- Fusion Compiler and Scripting experience.
Responsibilities
- Proficient in Verilog/System Verilog coding constructs.
- Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting).
- Experience with high speed PCIe designs and protocols.
- Experience with Industry standard interface protocols such as AXI, APB, etc.
- Experience with ARM Fabric IPs.
- Experience with IPXACT.
- Understanding of Computer Architecture fundamentals.
- Ability to write scripts using Python, Tcl, Perl etc.
- Experience in EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus.
- Proficiency with UPF (Low power intent).
- Proficiency in clock crossing techniques.
- Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals.
- Ensure customer satisfaction.
- Reporting to customers on daily or weekly progress effectively.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
Education Level
No Education Listed
