ASIC Core DFT Technical Leader - Scan, ATPG, Bist

Cisco•Maynard, MA

10d•$214,100 - $309,800

About The Position

As an ASIC Technical Leader, you will sit at the forefront of networking hardware innovation, directly shaping Cisco’s industry-defining Silicon One architecture. You will drive ground breaking Design-for-Test (DFT) strategies, bridging the gap between architecture, physical design, and post-silicon validation to ensure best-in-class quality for high-complexity ASICs. In this role, your technical leadership will directly fuel the next generation of best-of-breed routing and switching solutions deployed across global enterprises, data centers, and service providers.

Requirements

Bachelors + 12 years of related experience, or Masters + 8 years of related experience, or PhD + 5 years of related experience
Experience with Jtag protocols, Scan and BIST architectures, including memory BIST, boundary scan and post silicon debug.
Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
Prior verification experience including, System Verilog Logic Equivalency checking and validating the Test-timing of the design

Nice To Haves

Verilog design experience – developing custom DFT logic & IP integration; familiarity with functional verification
DFT CAD development – Test Architecture, Methodology and Infrastructure
Test Static Timing Analysis
Post silicon validation using DFT patterns.

Responsibilities

Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.
Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.

Benefits

medical, dental and vision insurance
a 401(k) plan with a Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees (non-exempt)
flexible vacation time off program (exempt)
80 hours of sick time off provided on hire date and each January 1st thereafter
up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer
annual bonuses (for non-sales roles)
performance-based incentive pay (for sales roles)