ASIC Core DFT Technical Leader
About The Position
The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. As an ASIC DFT Technical Leader, you will drive the definition, architecture, and implementation of cutting-edge Design-for-Test strategies across Cisco’s groundbreaking Silicon One portfolio. You will lead cross-functional integration from early-stage design through post-silicon validation, establishing scalable test logic, reusable code, and robust verification methodologies. Bridging physical design, DV, and system validation teams, you’ll oversee complex functional areas and shape end-to-end electrical specifications for industry-defining hardware. In this high-visibility leadership role, your innovations will directly enhance design quality, yield, and time-to-market for some of the most advanced networking silicon on the planet.
Requirements
- Bachelors + 12 years of related experience, or Masters + 8 years of related experience, or PhD + 5 years of related experience
- Experience with Jtag protocols, Scan and BIST architectures, including memory BIST, boundary scan and post silicon debug.
- Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
- Prior verification experience including, System Verilog Logic Equivalency checking and validating the Test-timing of the design
Nice To Haves
- Verilog design experience – developing custom DFT logic & IP integration; familiarity with functional verification
- DFT CAD development – Test Architecture, Methodology and Infrastructure
- Test Static Timing Analysis
- Post silicon validation using DFT patterns.
Responsibilities
- Drive the definition, architecture, and implementation of cutting-edge Design-for-Test strategies across Cisco’s groundbreaking Silicon One portfolio.
- Lead cross-functional integration from early-stage design through post-silicon validation, establishing scalable test logic, reusable code, and robust verification methodologies.
- Oversee complex functional areas and shape end-to-end electrical specifications for industry-defining hardware.
- Enhance design quality, yield, and time-to-market for advanced networking silicon.
Benefits
- medical, dental and vision insurance
- a 401(k) plan with a Cisco matching contribution
- paid parental leave
- short and long-term disability coverage
- basic life insurance
- Cisco restricted stock units
- 10 paid holidays per full calendar year
- 1 floating holiday for non-exempt employees
- 1 paid day off for employee’s birthday
- paid year-end holiday shutdown
- 4 paid days off for personal wellness
- 16 days of paid vacation time per full calendar year (non-exempt)
- flexible vacation time off program (exempt)
- 80 hours of sick time off provided on hire date and each January 1st thereafter
- up to 80 hours of unused sick time carried forward
- additional paid time away may be requested to deal with critical or emergency issues for family members
- Optional 10 paid days per full calendar year to volunteer
- annual bonuses (non-sales roles)
- performance-based incentive pay (sales roles)
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What This Job Offers
Job Type
Full-time
Career Level
Senior
