ASIC Core DFT Technical Lead - Scan, ATPG, Bist

Cisco • Maynard, MA

10d • $186,900 - $267,700

About The Position

As an ASIC Technical Lead, you will sit at the forefront of networking hardware innovation, directly shaping Cisco’s industry-defining Silicon One architecture. You will drive cutting-edge Design-for-Test (DFT) strategies, bridging the gap between front-end RTL, physical design, and post-silicon validation to ensure elite quality for some of the industry's most complex ASICs. In this role, your technical leadership and custom DFT solutions will directly fuel the next generation of best-of-breed routing and switching systems deployed across global enterprises, web-scale data centers, and service providers.

Requirements

• Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience
• Experience with Jtag protocols, Scan and BIST architectures, including memory BIST, boundary scan and post silicon debug.
• Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
• Prior verification experience including, System Verilog Logic Equivalency checking and validating the Test-timing of the design
• Prior experience with Tcl and Python/Perl.

Nice To Haves

• Verilog design experience – developing custom DFT logic & IP integration; familiarity with functional verification
• DFT CAD development – Test Architecture, Methodology and Infrastructure

Responsibilities

• Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
• Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.
• Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
• Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
• The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.

Benefits

• medical, dental and vision insurance
• a 401(k) plan with a Cisco matching contribution
• paid parental leave
• short and long-term disability coverage
• basic life insurance
• paid holidays
• floating holiday
• paid time off for employee’s birthday
• paid year-end holiday shutdown
• paid days off for personal wellness
• paid vacation time
• sick time off
• paid time away to deal with critical or emergency issues for family members
• paid days per full calendar year to volunteer
• annual bonuses

What This Job Offers

• Job Type: Full-time
• Career Level: Senior