Application Engineer, Customer Engagement

Cadence•San Jose, CA

6d•$124,485 - $191,100•Hybrid

About The Position

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This role involves utilizing an engineering background to provide pre-sales and/or post-sales technical customer support, including implementation, training, and maintenance support for Electronic Design Automation (EDA) and semiconductor intellectual property (IP). You will work directly with Cadence Research & Development to drive customer engagements, enhancing in-depth knowledge in nanometer design, unlocking unique expertise in digital design implementation, and leveling up communication, customer, and sales skills. You will deploy Cadence’s market-leading technologies in Synthesis, Place & Route (P&R), and Signoff to meet/exceed PPA (Power, Performance, Area) targets, achieve faster design closure, and turn customer design concepts into reality. The role requires understanding customer design requirements and methodology to drive adoption and proliferation of Cadence tools and technologies. You will guide customers on how to best utilize Cadence technologies to achieve their design goals at advanced nodes and meet project schedules. This includes conducting technical presentations and driving technical evaluations/benchmarks to success. Some telecommuting is permitted. Must be available to work on projects at various, unanticipated sites throughout the United States.

Requirements

Master’s degree in Electrical Engineering, Computer Engineering, or related field
Minimum one (1) year of experience in the job offered or in a related occupation
Industry standard synthesis and P&R tools used in the implementation of Application-Specific Integrated Circuits (ASICs)
Register Transfer Language (RTL) coding languages such as Verilog or VHDL
Design and timing constraints, power performance tradeoffs and power analysis
Amend and augment the flow as needed using Tcl and other programming skills to meet objectives and improve results and flows
Analog and mixed-signal design flow with Cadence environment, ideally using Virtuoso Studio tooling and associated design methodologies
Static Timing Analysis (STA) tool PrimeTime for debug and signoff
Logic Equivalence Checking (LEC) and Engineering Change Order (ECO) using Conformal to ensure the functional integrity of the design
Scan insertion, clock gating, multi-voltage and power domain handling to ensure the manufacturability and test coverage for reliability on the chip
Must be available to work on projects at various, unanticipated sites throughout the United States.

Responsibilities

Utilizing engineering background, provide pre-sales and/or post-sales technical customer support including implementation, training, and maintenance support for Electronic Design Automation (EDA) and semiconductor intellectual property (IP).
Work directly with Cadence Research & Development and drive customer engagements, enhancing in-depth knowledge in nanometer design, unlocking unique expertise in digital design implementation, and leveling up communication, customer, and sales skills.
Deploy Cadence’s market-leading technologies in Synthesis, Place & Route (P&R), and Signoff to meet/exceed their PPA (Power, Performance, Area) targets, achieve faster design closure, and turn their design concepts into reality.
Understand customer design requirements and methodology and drive adoption and proliferation of Cadence tools and technologies.
Guide customers on how to best utilize Cadence technologies to achieve their design goals at advanced nodes and meet project schedules.
Conduct technical presentations and drive technical evaluations/benchmarks to success.