Analog and Mixed Signal Design Engineer

BroadcomIrvine, CA
$109,700 - $175,500Onsite

About The Position

Broadcom’s Central Engineering Group is seeking an experienced Mixed-Signal Analog Design Engineer to join our world-class team. In this position, you will design advanced on-die Process, Voltage, and Temperature (PVT) monitoring IP. You will work across a wide range of cutting-edge technologies, including the industry's most advanced process nodes and applications.

Requirements

  • MS or PhD in Electrical Engineering
  • 6+ years of mixed-signal and analog design experience.
  • Deep knowledge of core analog concepts including gain, bandwidth, stability, device physics, circuit reliability, process variation, and the statistical analysis of Monte Carlo simulation results.
  • Strong understanding of layout effects on circuit performance.
  • Familiarity with Verilog modeling, digital circuits, and standard digital implementation flows.
  • Proficiency with Cadence Virtuoso and simulation platforms like Spectre, HSPICE, or PrimeSim.
  • Experience with Synopsys PrimeTime and Verilog simulators such as Xcelium or VCS.
  • Excellent communication and teamwork skills.
  • Proven ability to independently navigate complex, new, or unfamiliar engineering challenges.

Nice To Haves

  • Prior experience building and delivering mixed-signal IPs.
  • General familiarity with laboratory testing methodologies and common bench equipment to effectively guide lab teams.
  • Proficiency in scripting languages (Python, Perl, SKILL) to automate design and verification tasks.
  • Familiarity with ESD (Electrostatic Discharge) and latch-up design rules.
  • Silicon Failure Analysis (FA) and debugging skills.

Responsibilities

  • Design schematic architectures for analog and mixed-signal blocks, including bandgaps, ADCs, DACs, voltage regulators, comparators, and GPIOs.
  • Supervise layout design and verify post-layout design using SPICE simulations to ensure silicon success.
  • Build behavioral and gate-level models for IPs and validate functionality through Verilog simulations.
  • Create standard EDA tool views (including timing models), and author comprehensive datasheets and technical integration documents.
  • Establish post-silicon testing guidelines and oversee the validation process by analyzing and reviewing test data.

Benefits

  • Discretionary annual bonus
  • Competitive new hire equity grant
  • Annual equity awards
  • Medical plans
  • Dental plans
  • Vision plans
  • 401(K) participation
  • Company matching for 401(K)
  • Employee Stock Purchase Program (ESPP)
  • Employee Assistance Program (EAP)
  • Company paid holidays
  • Paid sick leave
  • Vacation time
  • Paid Family Leave (following applicable laws)
  • Other leaves of absence (following applicable laws)
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