AI Silicon Performance Modeling and Analysis Engineer

Intel•Santa Clara, CA

7d•Hybrid

About The Position

The AI Silicon Architecture and Performance Engineering team develops and maintains performance models for architecture exploration, design evaluation, scalability analysis, and performance projection for next-generation AI silicon products. These models provide early visibility into architectural tradeoffs, bottlenecks, and optimization opportunities before silicon is available. The engineer will drive AI silicon performance modeling, validation, architectural analysis, and stakeholder engagement. The role works closely with architects, performance stimulus generation teams, silicon design teams, and product stakeholders to evaluate and optimize AI silicon subsystems that determine platform scalability and performance. Areas of focus include AI SoC communication fabrics, memory subsystems, scale-up and scale-out interconnects, host-device memory paths, and end-to-end data movement infrastructure. The engineer uses SystemC/TLM-based modeling methodologies to produce insights that inform architecture and product decisions, while independently leading complex technical initiatives and serving as a performance expert across organizations. The position is an experienced hire based in Santa Clara, California, and is eligible for Intel’s hybrid work model, splitting time between the assigned Intel site and off-site. It is not eligible for Intel immigration sponsorship. The annual US target compensation range is $141,910 to $232,190, with individual pay determined by location and other job-related factors. Intel describes its total compensation package as including competitive pay, stock bonuses, and health, retirement, and vacation benefit programs.

Requirements

Bachelor’s or master’s degree in Computer Engineering, Electrical Engineering, Computer Science, or Electronics Engineering.
At least 6 years of industry experience in performance modeling, AI silicon architecture, SoC architecture, computer architecture, performance engineering, or a related domain.
Knowledge of SoC architecture, including on-chip communication fabrics, NoC concepts, high-speed interconnects, and scale-up/scale-out communication architectures.
Knowledge of memory subsystem architecture, including memory controllers, cache hierarchies, data movement, and latency/bandwidth characterization and performance bottleneck analysis.
Software development experience in C++.
Working proficiency in Python for automation, performance analysis, data processing, and visualization.
Hands-on experience with SystemC and Transaction-Level Modeling (TLM) methodologies.
Experience developing or validating performance models for AI accelerators, SoCs, CPUs, GPUs, networking products, or other complex hardware systems.
Experience performing architectural tradeoff analysis, performance debugging, and characterization studies.
Strong quantitative reasoning, data-driven decision-making, analytical problem-solving, communication, collaboration, technical presentation, and stakeholder management skills.
Ability to influence engineering decisions through rigorous analysis and technical credibility, operate independently in ambiguous problem spaces, and solve complex technical problems.
This position is not eligible for Intel immigration sponsorship.

Nice To Haves

Deep understanding of AI accelerator architectures and modern AI infrastructure.
Experience modeling memory, communication, interconnect, or scalability-related subsystems.
Experience with Network-on-Chip (NoC) architecture and interconnect performance analysis.
Understanding of scale-up and scale-out architectures used in modern AI computing platforms.
Familiarity with AI/ML workloads, large language models, distributed training, and inference environments.
Experience with performance stimulus generation methodologies and workload characterization.
Experience building automated dashboards and reporting solutions using Power BI, Tableau, Grafana, Plotly, or similar technologies.
Experience evaluating large-scale distributed AI systems and accelerator clusters.
Experience mentoring engineers and providing technical leadership in cross-functional environments.

Responsibilities

Develop, maintain, and enhance SystemC/TLM-based performance models for critical AI silicon subsystems.
Implement architectural features and capabilities as product requirements evolve; improve model fidelity, scalability, maintainability, and simulation performance.
Debug model issues and performance anomalies, perform root-cause analysis, and contribute to modeling infrastructure, methodologies, and best practices.
Model SoC fabrics, on-chip communication networks, memory controllers and subsystems, scale-up and scale-out controllers and fabrics, host-to-accelerator memory paths, local/host/remote memory access, and end-to-end data movement architectures.
Define and execute validation strategies, plans, regression suites, coverage methodologies, and quality metrics for model correctness and architectural accuracy.
Correlate modeled behavior with architectural expectations, reference simulations, performance projections, and available hardware measurements; investigate and resolve discrepancies.
Develop robust validation frameworks and continuously improve validation methodologies and model quality.
Design and execute performance studies across workloads, traffic patterns, and system configurations.
Analyze bandwidth utilization, latency, congestion, traffic distribution, buffering efficiency, resource utilization, and interactions among local, host, and remote memory domains.
Assess scale-up and scale-out scalability across larger deployment footprints; identify bottlenecks and quantify their impact on throughput and efficiency.
Conduct architectural tradeoff studies and provide performance-driven recommendations that influence architecture and product decisions.
Develop frameworks and automated workflows for large-scale performance data generation, collection, processing, correlation, and reporting.
Build performance dashboards and visualization tools, define and track KPIs and architectural metrics, and use Python-based analysis to generate actionable insights.
Partner with architecture, performance stimulus generation, silicon design, and product teams; lead technical discussions and review architectural proposals.
Present performance studies, technical findings, and recommendations to engineering leadership, and influence decisions through data-backed analysis.
Improve modeling methodologies, simulation efficiency, and analysis workflows; identify automation opportunities and establish best practices.
Contribute to technical mentoring and knowledge sharing, support junior engineers, and help cultivate technical excellence and continuous improvement.