AI Silicon Performance Modeling and Analysis Engineer

Intel Corporation•Santa Clara, CA

8d•$141,910 - $232,190•Hybrid

About The Position

The AI Silicon Architecture and Performance Engineering team develops and maintains performance models that support architecture exploration, design evaluation, scalability analysis, and performance projections for next-generation AI silicon. The models provide early insight into architectural tradeoffs, bottlenecks, and optimization opportunities before silicon is available. The engineer will drive AI silicon performance modeling, validation, architectural analysis, and stakeholder engagement. The role works with architects, performance stimulus generation teams, silicon design teams, and product stakeholders to evaluate and optimize subsystems affecting AI silicon platform scalability and performance. It focuses on SystemC/TLM-based modeling and analysis of SoC communication fabrics, memory subsystems, scale-up and scale-out interconnects, host-device memory paths, and end-to-end data movement infrastructure. The position combines software development expertise, architecture knowledge, analytical problem-solving, and cross-functional technical leadership. The engineer is expected to independently lead complex technical initiatives and serve as a performance expert across organizations. The role is based in a hybrid work model, splitting time between the assigned Intel site and off-site work.

Requirements

Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, Computer Science, or Electronics Engineering.
At least 6 years of industry experience in performance modeling, AI silicon architecture, SoC architecture, computer architecture, performance engineering, or related domains.
At least 6 years of experience with SoC architecture, including on-chip communication fabrics, NoC concepts, high-speed interconnects, and scale-up/scale-out communication architectures.
At least 6 years of experience with memory subsystem architecture, including memory controllers, cache hierarchies, data movement, latency and bandwidth characterization, and performance bottleneck analysis.
At least 6 years of software development experience in C++.
Working proficiency in Python for automation, performance analysis, data processing, and visualization.
Hands-on experience with SystemC and Transaction-Level Modeling (TLM) methodologies.
Experience developing or validating performance models for AI accelerators, SoCs, CPUs, GPUs, networking products, or other complex hardware systems.
Experience performing architectural tradeoff analysis, performance debugging, and characterization studies.
Strong quantitative reasoning and data-driven decision-making skills.
Strong analytical and problem-solving skills, communication and collaboration skills, and technical presentation and stakeholder management skills.
Ability to influence engineering decisions through rigorous analysis and technical credibility, operate independently in ambiguous problem spaces, and solve complex technical problems.

Nice To Haves

Deep understanding of AI accelerator architectures and modern AI infrastructure.
Experience modeling memory, communication, interconnect, or scalability-related subsystems.
Experience with Network-on-Chip (NoC) architecture and interconnect performance analysis.
Understanding of scale-up and scale-out architectures used in modern AI computing platforms.
Familiarity with AI/ML workloads, large language models, distributed training, and inference environments.
Experience with performance stimulus generation methodologies and workload characterization.
Experience building automated dashboards and reporting solutions using Power BI, Tableau, Grafana, Plotly, or similar technologies.
Experience evaluating large-scale distributed AI systems and accelerator clusters.
Experience mentoring engineers and providing technical leadership in cross-functional environments.

Responsibilities

Develop, maintain, and enhance SystemC/TLM-based performance models for critical AI silicon subsystems.
Implement architectural features and capabilities based on evolving product requirements, and improve model fidelity, scalability, maintainability, and simulation performance.
Model SoC fabrics and on-chip communication networks, memory controllers and subsystems, scale-up and scale-out controllers and fabrics, host CPU-to-accelerator memory paths, local, host, and remote memory access paths, and end-to-end data movement architectures.
Debug model issues and performance anomalies, perform root-cause analysis, and contribute to modeling infrastructure, methodologies, and best practices.
Define and execute validation strategies for model correctness and architectural accuracy, including validation plans, regression suites, coverage methodologies, and quality metrics.
Correlate modeled behavior with architectural expectations, reference simulations, performance projections, and available hardware measurements; investigate discrepancies and improve validation frameworks and model quality.
Design and execute performance studies across workloads, traffic patterns, and system configurations.
Analyze fabric, memory-system, and data-movement performance, including bandwidth utilization, latency, congestion, traffic distribution, buffering efficiency, and resource utilization.
Characterize local, host, and remote memory interactions and assess scale-up and scale-out scalability across deployment footprints.
Identify and quantify performance bottlenecks, conduct architectural tradeoff studies, and provide performance-driven recommendations for architecture and product decisions.
Develop frameworks and workflows for large-scale performance data generation, collection, processing, correlation, and reporting.
Create performance dashboards and visualization tools, define and track KPIs and architectural metrics, and use Python-based analysis to derive actionable insights.
Partner with architecture, stimulus generation, silicon design, and product stakeholders; lead technical discussions and review architectural proposals with performance-driven feedback.
Present performance studies, findings, and recommendations to engineering leadership and influence decisions through data-backed analysis.
Improve modeling methodologies, simulation efficiency, and analysis workflows; identify automation opportunities and establish best practices.
Contribute to mentoring and knowledge sharing, support junior engineers and team growth, and promote technical excellence and continuous improvement.