Advanced Packaging Technology & Integration Leader

Applied Materials•Santa Clara, CA

6d•$200,000 - $275,000

About The Position

Applied Materials is seeking an Advanced Packaging Technology & Integration Leader to lead development of next-generation semiconductor packaging and 3D integration technologies. The role combines deep technical expertise, first-principles problem solving, semiconductor process integration, and technical leadership. The successful candidate will develop new technologies by understanding fundamental physics, materials, interfaces, processes, and integration constraints, rather than only optimizing established process flows. The role spans hybrid bonding, through-silicon vias (TSVs), advanced thermal materials and thermal management, interposers, bridge-die technologies, and heterogeneous integration. The leader will guide cross-functional teams across materials, unit-process development, integration, device and package architecture, modeling, characterization, equipment, and manufacturing. Work includes developing differentiated technologies, establishing roadmaps, defining experiments and integration strategies, and advancing concepts through proof of principle, integrated demonstration, and manufacturable solutions. The position also involves mentoring technical staff, setting technical direction, communicating complex issues to engineering teams and executives, engaging with customers and industry partners, and translating future architecture and scaling requirements into technology-development programs. The position is based in Santa Clara, California, offers a salary range of $200,000 to $275,000, requires travel 10% of the time, and is eligible for relocation.

Requirements

Advanced degree in Materials Science, Chemical Engineering, Electrical Engineering, Mechanical Engineering, Applied Physics, or a closely related discipline, or equivalent demonstrated semiconductor technology-development expertise; an advanced degree is preferred.
Demonstrated experience developing semiconductor technologies or integration schemes from early concept through experimental validation.
Deep understanding of semiconductor process integration.
Strong expertise in several of the following areas, with broad understanding across the remainder: hybrid bonding, TSV technology, 2.5D/3D integration, interposers, bridge die, chiplet integration, thermal-management materials, thin-wafer processing, wafer/die bonding, advanced metallization, CMP and surface preparation, mechanical stress and wafer warpage, and semiconductor/package reliability.
Ability to reason from fundamental physics and materials behavior when established solutions are insufficient.
Demonstrated ability to design experiments that distinguish between competing physical mechanisms and accelerate technical learning.
Strong record of leading complex, multidisciplinary semiconductor technology-development programs.
Demonstrated ability to mentor technical teams and influence organizations beyond direct reporting relationships.
Excellent written and verbal communication skills, including the ability to communicate from detailed engineering reviews through executive-level technology strategy.

Nice To Haves

Experience developing technology for AI/HPC, HBM, chiplets, logic-memory integration, or other high-performance heterogeneous systems.
Experience working across the semiconductor ecosystem, including device manufacturers, foundries, OSATs, equipment companies, material suppliers, or research organizations.
Experience translating future device/package architectures into semiconductor process and equipment requirements.
Track record of technical innovation demonstrated through patents, publications, technology transfers, or successful product/process introductions.
Strong understanding of interactions among electrical performance, power delivery, thermal management, mechanical integrity, manufacturability, cost, and yield.
Experience moving technology from pathfinding or R&D into product development or manufacturing.

Responsibilities

Develop differentiated semiconductor packaging technologies from first principles, translating understanding of materials, interfaces, mechanics, thermal behavior, electrical performance, and process physics into practical solutions.
Identify technology limitations in future AI/HPC, memory, and heterogeneous-integration architectures and develop approaches to overcome them.
Convert early concepts into experimentally testable structures, integration flows, and technology demonstrations.
Establish technology roadmaps linking future device and package requirements to materials, processes, equipment capabilities, and integration schemes.
Evaluate competing technical approaches and recommend solutions based on engineering trade-offs.
Provide technical leadership across hybrid bonding, TSVs, 2.5D and 3D integration, interposers, bridge-die architectures, chiplets, heterogeneous integration, redistribution and high-density interconnects, and thermal management.
Develop complete process-integration strategies that account for interactions among deposition, etch, CMP, cleans, bonding, lithography, metallization, wafer thinning, and packaging operations.
Define integration experiments and learning cycles to identify root causes and fundamental process limitations.
Manage trade-offs involving thermal budget, contamination, stress, topology, alignment, electrical performance, yield, and reliability across process modules.
Drive technologies from concept through proof of principle and integrated demonstration to manufacturable solutions.
Lead multidisciplinary teams of process engineers, integration engineers, materials scientists, modeling engineers, equipment engineers, and external collaborators.
Set technical direction, mentor senior technical staff, and develop future technical leaders.
Foster a culture in which hypotheses are tested through physics, modeling, data, and experimentation.
Lead technical reviews and communicate complex technical issues to engineering teams and senior executives.
Engage with logic, memory, foundry, OSAT, and AI/HPC customers to understand future integration challenges.
Translate customer architecture and scaling requirements into technology-development programs.
Collaborate with universities, research organizations, material suppliers, equipment partners, and ecosystem companies.
Represent the organization as a technical authority in advanced packaging and heterogeneous integration.