Advanced Packaging Engineer — Fiber Array Integration

Cspeed • Palo Alto, CA

3d • Onsite

About The Position

Cspeed IO is a stealth start up backed by Sutter Hill Ventures and Atreides Capital - headquartered in Palo Alto, CA. Our executive team has a demonstrated track record of building and scaling category-defining semiconductor and infrastructure businesses at companies like Broadcom, Lumentum, Tesla, Apple, Samsung, Intel, and VMware.
Cspeed IO is developing next-generation optical semiconductor solutions for the AI infrastructure market, focused on enabling true “scale-up” architectures. Our mission is to replace traditional copper interconnects with advanced fiber-optic technologies that overcome the limitations of existing optics solutions and architectures.
This position owns the detachable optical interface for CspeedIO optical engines: the on-package element, the coupling optics, the alignment features, and the high-volume assembly process that joins fiber to engine without per-unit active alignment.
A permanently bonded fiber array constrains the downstream flow in three respects: the engine cannot be optically qualified before fiber attach, a single failed channel scraps an assembly containing multiple high-value die, and manual fiber handling limits automation. A detachable interface addresses all three, enabling known-good-engine qualification, rework of failed units, and independent build and test of the fiber subassembly.
Scope runs from interface architecture and tolerance budgeting through qualification and transfer of the production process to our assembly partners.

Requirements

• BS/MS/PhD in Optical Engineering, Mechanical Engineering, Physics, Materials Science, or equivalent practical experience.
• 6+ years in optical or photonic packaging or optical interconnect, including ownership of an optical interface taken from development into production or pilot production.
• Direct experience with fiber-optic connector technology: ferrules and guide-pin alignment, expanded-beam or lensed interfaces, and mate/demate qualification.
• Tolerance stack analysis and GD&T for sub-micron optical interfaces, including statistical rather than worst-case methods.
• Working knowledge of fiber-to-chip coupling physics: mode field matching, collimation and beam expansion, angular and lateral sensitivity, polarization effects, and return loss.
• Hands-on optical metrology: tunable sources, power meters, insertion and return loss measurement, and interferometric or confocal inspection of interfaces.
• Experience qualifying an optical interface against connector reliability standards.
• Willingness to work in both laboratory and production environments, and professional English across distributed sites and time zones.

Nice To Haves

• Detachable or pluggable optical interfaces for co-packaged optics, on-board optics, or mid-board optical modules.
• Passive alignment using lithographically defined features; wafer-level optics; micro-lens array design or integration.
• Reflow-survivable optical assemblies, including interfaces qualified through a 260 °C profile.
• Precision manufacturing processes for connector hardware: ferrule molding, precision metal stamping or forming, glass forming, or micro-machining.
• Lens design and tolerancing (Zemax, CODE V, or equivalent).
• Silicon photonics: surface and grating couplers, facet preparation, and PIC-side alignment feature definition.
• Particle and contamination control in optical assembly environments.
• Active alignment process development experience.
• Standards or MSA participation.
• Transfer of a novel optical process into an OSAT without an established reference process.

Responsibilities

• Detachable interface architecture: Define the location of the detachability point and the partition between the permanently attached on-package element and the mateable plug. Define the coupling optics for the detachable path, including expanded-beam or collimated design, lens prescription and tolerancing, and the surface- versus edge-coupling trade-off. Establish the alignment strategy — lithographically defined PIC features, precision mechanical datums, guide-pin or V-groove references — and the passive alignment capability it delivers.
• Tolerance, loss, and repeatability budgeting: Own the insertion loss budget, including mated-interface penalty, per-channel uniformity across the array, and return loss. Develop the tolerance stack from PIC feature placement through package assembly to plug geometry using statistical methods, with a per-port loss distribution as the deliverable. Specify and demonstrate repeatability across mate and demate cycles, and interchangeability across plug units and suppliers. Quantify positional and angular sensitivity and define the budget the mechanical design must hold.
• High-volume manufacturing readiness: Eliminate per-unit active alignment from the engine assembly flow. Where it cannot be eliminated, relocate it to a separately built and tested subassembly. Qualify reflow survivability of the on-package element and compatibility with the assembly flows our OSATs operate. Define automated mating requirements: insertion force, blind-mate behavior, retention, and hands-off assembly tooling. Establish Cpk on passive placement and coupling loss, with associated SPC limits, yield reporting, and failure taxonomy. Maintain the per-port cost and cycle-time model covering alignment, mating and cleaning time, rework, and connector BOM.
• Contamination control and serviceability: Define the contamination control strategy: dust caps, handling protocol, cleaning process and tooling, inspection criteria, and particle-size sensitivity for the selected beam geometry. Define serviceability requirements: authorized personnel, permitted mating cycles, required training and tooling, and diagnostic criteria distinguishing contamination from mechanical damage. Define the rework and RMA flow for the optical interface.
• Reliability and qualification: Qualify the mated interface. Characterize insertion loss drift across mating cycles and environmental exposure. Conduct root-cause analysis of degradation across coupling optics, alignment features, latch mechanics, and contamination.
• Standards, supply chain, and test enablement: Monitor and, where appropriate, participate in relevant standards and consortium activity (Open CPX MSA, IEC and TIA connector standards, OIF) in support of interoperability. Qualify and manage connector and FAU suppliers, including incoming inspection criteria, pitch and feature tolerance, cleanliness, and lot-to-lot consistency. Coordinate with test architecture to ensure the interface delivers known-good-engine test capability.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior