Advanced ASIC FPGA Verification Engineer (Sign-on Bonus Available)

General Dynamics Mission Systems, Inc • Scottsdale, AZ

6d • $122,785 - $136,215 • Hybrid

About The Position

General Dynamics Mission Systems is hiring an Advanced ASIC FPGA Verification Engineer for its Scottsdale, Arizona team. The role is responsible for the definition, design, verification, and documentation of ASIC and/or FPGA developments. The engineer determines architecture, system simulation, and detailed design approaches; defines module interfaces and device design and simulation; and creates test and simulation plans that establish functional criteria. The role verifies test results, analyzes performance, may review vendor capabilities and simulation tools, and contributes to improvement of ASIC/FPGA organizational processes. It supports the creation of technical engineering products using appropriate standards, processes, procedures, and tools throughout the ASIC/FPGA development life cycle. The engineer independently determines approaches to solutions, contributes to major programs and projects, and plans and executes related project tasks. The position may provide leadership or direction to lower-level employees.

The successful candidate will work in a team environment, learn new skills to meet verification goals, and operate under limited direction. The role includes regular contact with senior internal work groups, project leaders and other Engineering professionals, and project teams across the company, as well as some contact with external customers. Candidates must be able to obtain a U.S. Department of Defense TS/SCI security clearance within a reasonable time after hire. U.S. citizenship is required due to the nature of the work.

The position is fully on-site or hybrid/flex, as mutually agreed. The employer describes an exciting career path with continuous learning and development, research-oriented work with award-winning teams developing solutions for national security, and flexible schedules including the option of every other Friday off under a 9/80 schedule. The listed salary range is USD $122,785–$136,215 per year; actual pay may vary based on experience and other factors.

Requirements

• Bachelor’s degree in Electrical or Computer Engineering, or a related Science, Engineering, Technology, or Mathematics field, and 5 or more years of job-related experience; alternatively, a master’s degree and 3 or more years of job-related experience.
• Must be able to obtain a U.S. Department of Defense TS/SCI security clearance within a reasonable amount of time from date of hire.
• U.S. citizenship is required.
• Ability to operate in a team environment and learn new skills to accomplish verification goals.
• Proficient understanding of ASIC/FPGA engineering concepts, principles, and theories.
• Proficient knowledge of ASIC/FPGA design principles, techniques, and the design process.
• Proficient in Microsoft Office applications.
• Proficient written and verbal communication skills.
• Ability to think creatively and multitask.
• Proficient at communicating issues, impacts, and corrective actions.
• In-depth experience with RTL simulation tools such as Siemens Mentor Graphics Questa or ModelSim, or equivalent, in a Linux environment.
• In-depth knowledge of SystemVerilog object-oriented programming and the Universal Verification Methodology (UVM).
• Understanding of UVM testbench architectures and comfort using and developing UVM agents and bus functional models.
• Understanding of different types of coverage and use of cover classes and cover points.
• Experience with predictive testbench components, functional coverage, assertions, and constrained-random testing.
• Experience with the Register Abstraction Layer.
• Familiarity with requirements-based verification, requirement tracing, and development of requirement verification strategies.
• Experience with scripting languages such as Linux shell scripts, TCL, and Python.
• Familiarity with formal verification tools, code coverage, and writing waivers.
• Clear understanding of embedded micro-processing systems, FPGA design and verification using VHDL, and digital circuit analysis and design.
• Collaborative, creative approach to technical problem solving.
• Effective communication and presentation skills.

Nice To Haves

• Familiarity with Questa Verification IP (QVIP).
• Experience developing UVM testbenches for designs implemented in Xilinx devices with Xilinx IP and SoCs.
• Experience with AXI protocols, PCIe, SpaceWire, and Ethernet interfaces.
• Experience with DSP functions and common signal-processing components.
• Familiarity with debugging FPGA/ASIC hardware and assisting with hardware/software integration.
• Familiarity with GitLab continuous integration features.
• Experience designing high-speed interfaces and complex memory designs.
• Commitment to ongoing professional development for yourself and others.
• Ability to identify opportunities to apply AI for continuous improvement and innovation.
• Keeps abreast of technology trends and demonstrates awareness of business objectives and Engineering’s role in achieving them.

Responsibilities

• Define, design, verify, and document ASIC and/or FPGA developments.
• Determine architecture, system simulation, and detailed design approaches.
• Define module interfaces and all aspects of device design and simulation.
• Create test and simulation plans that establish functional criteria.
• Verify test results and analyze performance.
• Review vendor capabilities and simulation tools, as needed.
• Participate in improving ASIC/FPGA organizational processes.
• Support generation of technical engineering products using appropriate standards, processes, procedures, and tools throughout the ASIC/FPGA development life cycle.
• Independently determine approaches to solutions and contribute to major programs and projects.
• Plan and execute project tasks related to ASIC/FPGA development and verification.
• May provide leadership and/or direction to lower-level employees.
• Work with project leaders, Engineering professionals, cross-company project teams, and, at times, external customers.

Benefits

• 401(k) matching
• Flexible schedules, including the option of every other Friday off under a 9/80 schedule
• Flex time off
• Paid parental leave
• Healthcare benefits
• Health and wellness programs
• Employee resource and social groups
• Continuous learning and development opportunities
• Sign-on bonus availability is indicated in the job title.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior