Advanced ASIC FPGA Verification Engineer (Sign-on Bonus Available)

General Dynamics Mission Systems • Scottsdale, AZ

5d • Hybrid

About The Position

General Dynamics Mission Systems is hiring an Advanced ASIC FPGA Verification Engineer for its Scottsdale, Arizona team. The role is responsible for defining, designing, verifying, and documenting ASIC and/or FPGA developments. It determines architecture, system simulation, and detailed design approaches; defines module interfaces and device design and simulation; creates test and simulation plans; and verifies results and analyzes performance. The engineer supports technical engineering products throughout the ASIC/FPGA development life cycle, contributes to organizational process improvements, and may provide direction to lower-level employees. The position works under limited direction, independently determines approaches to solutions, and plans and executes project tasks. The workplace is fully on-site or hybrid/flex, as mutually agreed.

Candidates must hold a bachelor's degree in Electrical or Computer Engineering or a related STEM field and have at least five years of job-related experience, or hold a master's degree and have at least three years of job-related experience. Candidates must be able to obtain a U.S. Department of Defense TS/SCI clearance within a reasonable time after hire. U.S. citizenship is required.

The role emphasizes RTL simulation and SystemVerilog/UVM verification, including testbench architecture, agents, bus functional models, coverage, assertions, constrained-random testing, and requirements-based verification. The engineer works with scripting and verification tools in a Linux environment and may use formal verification, code coverage, and related tools. The team values technical problem-solving, collaboration, communication, adaptability, and continued professional development.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related Science, Engineering, Technology, or Mathematics field, plus at least 5 years of job-related experience; or a master's degree plus at least 3 years of job-related experience.
• Ability to obtain a U.S. Department of Defense TS/SCI security clearance within a reasonable amount of time from hire.
• U.S. citizenship.
• Proficient understanding of ASIC/FPGA engineering concepts, principles, theories, design principles, and design processes.
• Ability to operate in a team environment and learn new skills to accomplish verification goals.
• Proficient written and verbal communication, including communicating issues, impacts, and corrective actions.
• Ability to think creatively and multitask.
• Proficiency with Microsoft Office applications.
• Ability to work under limited direction and maintain regular contact with senior internal work groups, project leaders, engineering professionals, and project teams; some external customer contact.
• In-depth experience with RTL simulation tools such as Siemens Mentor Graphics Questa or ModelSim, or equivalent, in a Linux environment.
• In-depth knowledge of SystemVerilog object-oriented programming and Universal Verification Methodology (UVM).
• Understanding of UVM testbench architectures and experience using and developing UVM agents and bus functional models.
• Understanding of coverage types and use of cover classes and cover points.
• Experience with predictive testbench components, functional coverage, assertions, and constrained-random testing.
• Experience with the Register Abstraction Layer.
• Familiarity with requirements-based verification, requirements tracing, and developing requirement verification strategies.
• Experience with scripting languages such as Linux shell scripts, TCL, or Python.

Nice To Haves

• Familiarity with formal verification tools, code coverage, and writing waivers.
• Familiarity with Questa Verification IP (QVIP).
• Experience developing UVM testbenches for designs implemented in Xilinx devices with Xilinx IP and SoCs.
• Familiarity with AXI protocols, PCIe, SpaceWire, and Ethernet interfaces.
• Familiarity with DSP functions and common signal-processing components.
• Familiarity with debugging FPGA/ASIC hardware and assisting with hardware/software integration.
• Familiarity with GitLab continuous integration features.
• Understanding of embedded microprocessing systems, FPGA design and verification using VHDL, and digital circuit analysis and design.
• Experience designing high-speed interfaces and complex memory designs.
• Commitment to ongoing professional development for yourself and others.
• Ability to identify opportunities to apply AI for continuous improvement and innovation.

Responsibilities

• Define, design, verify, and document ASIC and/or FPGA developments.
• Determine architecture, system simulation, and detailed design approaches.
• Define module interfaces and device design and simulation details.
• Create test and simulation plans that establish functional criteria.
• Verify test results and analyze performance.
• Review vendor capabilities and simulation tools, as needed.
• Participate in improving ASIC/FPGA organizational processes.
• Support the generation of technical engineering products using appropriate standards, processes, procedures, and tools throughout the ASIC/FPGA development life cycle.
• Plan and execute project tasks related to ASIC/FPGA development and verification.
• Independently determine approaches to solutions and contribute to major programs and projects.
• Provide leadership and/or direction to lower-level employees, as needed.

Benefits

• 401(k) matching
• Flexible schedules, including an optional 9/80 schedule with every other Friday off
• Flex time off
• Paid parental leave
• Healthcare benefits
• Health and wellness programs
• Employee resource and social groups
• Competitive benefits

What This Job Offers

• Job Type: Full-time
• Career Level: Senior