Advanced ASIC FPGA Verification Engineer (Sign-on Bonus Available)

General Dynamics Mission Systems, Inc • Scottsdale, AZ

6d • $122,785 - $136,215

About The Position

General Dynamics Mission Systems is hiring an Advanced ASIC FPGA Verification Engineer to define, design, verify, and document ASIC and/or FPGA developments. The role determines architecture, system simulation, and detailed design approaches; defines module interfaces and device design and simulation details; creates test and simulation plans; verifies results and analyzes performance; and supports engineering products throughout the ASIC/FPGA development life cycle. The engineer may review vendor capabilities and simulation tools, contribute to organizational process improvements, provide direction to lower-level employees, and plan and execute project tasks.

The position calls for a collaborative engineer who can work under limited direction, contribute to major programs and projects, communicate technical issues and corrective actions, and learn new skills to meet verification goals. The position is part of the Scottsdale, Arizona team and may be fully remote, on-site, or hybrid/flex, as mutually agreed. A 9/80 schedule is available, with every other Friday off if desired.

Candidates must be able to obtain a U.S. Department of Defense TS/SCI clearance within a reasonable time after hire and must be U.S. citizens. The listed annual salary range is $122,785–$136,215; actual pay may vary based on experience and other factors. The posting remains open until the position is filled.

Requirements

• Bachelor’s degree in Electrical or Computer Engineering, or a related Science, Engineering, Technology, or Mathematics field, and 5+ years of job-related experience; alternatively, a master’s degree and 3 years of job-related experience.
• Must be able to obtain a U.S. Department of Defense TS/SCI security clearance within a reasonable amount of time from date of hire.
• U.S. citizenship is required.
• Ability to operate in a team environment and learn new skills to accomplish verification goals.
• Proficiency in ASIC/FPGA engineering concepts, principles, theories, design principles, and design processes.
• Proficiency in Microsoft Office applications.
• Strong written and verbal communication skills, including communicating issues, impacts, and corrective actions.
• Ability to think creatively and multitask.
• In-depth experience with RTL simulation tools such as Siemens Mentor Graphics Questa or ModelSim, or equivalent, in a Linux environment.
• In-depth knowledge of SystemVerilog object-oriented programming and UVM.
• Understanding of UVM testbench architectures and experience using and developing UVM agents and bus functional models.
• Understanding of coverage types and use of cover classes and cover points.
• Experience with predictive testbench components, functional coverage, assertions, and constrained-random testing.
• Experience with the Register Abstraction Layer.
• Familiarity with requirements-based verification, requirements tracing, and developing verification strategies.
• Experience with scripting languages such as Linux shell scripts, TCL, or Python.
• Familiarity with formal verification tools, code coverage, and writing waivers.
• Works under limited direction and maintains awareness of business objectives and Engineering’s role in achieving them.
• Must be able to maintain regular contact with senior internal work groups and work with project leaders, engineering professionals, and project teams.

Nice To Haves

• Familiarity with Questa Verification IP (QVIP).
• Experience developing UVM testbenches for designs implemented in Xilinx devices with Xilinx IP and SoCs.
• Experience with AXI protocols, PCIe, Space Wire, and Ethernet interfaces.
• Experience with DSP functions and common signal-processing components.
• Familiarity with debugging FPGA/ASIC hardware and assisting with hardware/software integration.
• Familiarity with GitLab Continuous Integration features.
• Understanding of embedded micro-processing systems, FPGA design and verification using VHDL, and digital circuit analysis and design.
• Experience designing high-speed interfaces and complex memory designs.
• Collaborative, creative approach to technical problem solving and effective communication and presentation skills.
• Commitment to ongoing professional development for oneself and others.
• Ability to identify opportunities to apply AI for continuous improvement and innovation.
• Proficiency in keeping abreast of technology trends.

Responsibilities

• Define, design, verify, and document ASIC and/or FPGA developments.
• Determine architecture, system simulation, and detailed design approaches.
• Define module interfaces and device design and simulation details.
• Create test and simulation plans that establish functional criteria.
• Verify test results and analyze performance.
• Review vendor capabilities and simulation tools as needed.
• Participate in improving ASIC/FPGA organizational processes.
• Support generation of technical engineering products using appropriate standards, processes, procedures, and tools throughout the ASIC/FPGA development life cycle.
• Provide leadership and/or direction to lower-level employees as needed.
• Independently determine approaches to solutions and contribute to major programs and projects.
• Plan and execute project tasks related to the duties above.
• Communicate issues, impacts, and corrective actions and collaborate with project leaders, engineering colleagues, project teams, and occasionally external customers.

Benefits

• 401(k) matching
• Flexible schedules, including an optional 9/80 schedule with every other Friday off
• Flex time off
• Paid parental leave
• Healthcare benefits
• Health and wellness programs
• Employee resource and social groups
• Opportunities for continuous learning and development

What This Job Offers

• Job Type: Full-time
• Career Level: Senior