Advanced ASIC FPGA Verification Engineer (Sign-on Bonus Available)

General Dynamics Mission Systems • Scottsdale, AZ

5d

About The Position

General Dynamics Mission Systems is hiring an Advanced ASIC FPGA Verification Engineer for its Scottsdale, Arizona team. The position supports the definition, design, verification, and documentation of ASIC and/or FPGA developments, including architecture, system simulation, detailed design, module interfaces, device simulation, test planning, and performance analysis. The role contributes to major programs and projects, supports engineering products across the ASIC/FPGA development life cycle, and may provide direction to lower-level employees. The engineer works under limited direction and collaborates with engineering colleagues, project teams, and some external customers.

The role calls for experience with RTL simulation, SystemVerilog, UVM testbench architecture and components, functional coverage, assertions, constrained-random testing, and requirements-based verification. Helpful experience includes formal verification tools, scripting, Xilinx devices and IP, common interface protocols, FPGA/ASIC hardware debugging, and hardware/software integration. Candidates must be U.S. citizens and able to obtain a U.S. Department of Defense TS/SCI clearance within a reasonable time after hire.

The position may be fully remote, on-site, or hybrid/flex, as mutually agreed. The company offers a flexible 9/80 schedule, including every other Friday off if desired, along with competitive benefits and opportunities for learning and development.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related Science, Engineering, Technology, or Mathematics field, plus at least 5 years of job-related experience; or a master’s degree plus at least 3 years of job-related experience.
• Must be able to obtain a U.S. Department of Defense TS/SCI security clearance within a reasonable amount of time after hire; selected applicants are subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information.
• U.S. citizenship is required due to the nature of the work.
• Proficient use and understanding of ASIC/FPGA engineering concepts, principles, theories, design principles, and design processes.
• Ability to operate in a team environment and learn new skills to accomplish verification goals.
• Proficient written and verbal communication, including the ability to communicate issues, impacts, and corrective actions.
• Ability to think creatively and multitask.
• Proficiency in Microsoft Office applications.
• Awareness of technology trends and business objectives, and engineering’s role in achieving them.
• Ability to work under limited direction and interact with senior internal work groups, project leaders, engineering professionals, and project teams.

Nice To Haves

• In-depth experience with RTL simulation tools such as Siemens Mentor Graphics Questa or ModelSim, or equivalent, in a Linux environment.
• In-depth knowledge of SystemVerilog object-oriented programming and the Universal Verification Methodology (UVM).
• Understanding of UVM testbench architectures and experience using or developing UVM agents and bus functional models.
• Understanding of coverage types and use of cover classes and cover points.
• Experience with predictive testbench components, functional coverage, assertions, and constrained-random testing.
• Experience with the Register Abstraction Layer.
• Familiarity with requirements-based verification, requirements tracing, and developing requirements verification strategies.
• Experience with scripting languages such as Linux shell scripting, TCL, or Python.
• Familiarity with formal verification tools, code coverage, and writing waivers.
• Familiarity with Questa Verification IP (QVIP).
• Experience developing UVM testbenches for designs implemented in Xilinx devices with Xilinx IP and SoCs.
• Experience with AXI protocols, PCIe, SpaceWire, and Ethernet interfaces.
• Experience with DSP functions and common signal-processing components.
• Familiarity with debugging FPGA/ASIC hardware and assisting with hardware/software integration.
• Familiarity with continuous integration features of GitLab.
• Clear understanding of embedded microprocessor systems, FPGA design and verification using VHDL, and digital circuit analysis and design.
• Experience designing high-speed interfaces and complex memory designs.
• Collaborative, creative approach to technical problem solving, with effective communication and presentation skills.
• Commitment to ongoing professional development for oneself and others.
• Ability to identify opportunities to apply AI for continuous improvement and innovation.

Responsibilities

• Define, design, verify, and document ASIC and/or FPGA developments.
• Determine architecture, system simulation, and detailed design approaches.
• Define module interfaces and aspects of device design and simulation.
• Create test and simulation plans that establish functional criteria.
• Verify test results and analyze performance.
• Review vendor capabilities and simulation tools as needed.
• Participate in improving ASIC/FPGA organizational processes.
• Support the generation of technical engineering products using appropriate standards, processes, procedures, and tools throughout the ASIC/FPGA development life cycle.
• Provide leadership and/or direction to lower-level employees as needed.
• Independently determine approaches to solutions and contribute to major programs and projects.
• Plan and execute project tasks related to the responsibilities above.
• Work collaboratively in a team environment, communicate issues and corrective actions, and maintain contact with internal work groups, project teams, and some external customers.

Benefits

• 401(k) matching
• Flexible schedules, including an optional 9/80 schedule with every other Friday off
• Flex time off
• Paid parental leave
• Healthcare benefits
• Health and wellness programs
• Employee resource and social groups
• Opportunities for continuous learning and development

What This Job Offers

• Job Type: Full-time
• Career Level: Senior