Yield Enhancement Engineer

TSMC • Washington, DC

1h • $87,000 - $115,580 • Onsite

About The Position

TSMC Washington is hiring a Yield Enhancement Engineer to identify, analyze, and eliminate physical or electrical defect sources that limit wafer yields. The role works within a high-volume manufacturing cleanroom environment and uses advanced metrology, data analytics, and cross-functional collaboration to prevent production excursions and optimize mature CMOS process nodes.

The engineer supports defect reduction and yield improvement through root-cause analysis, physical failure analysis, statistical monitoring, electrical characterization, defect-reduction roadmaps, and continuous improvement. The position also owns inline defect inspection, review, and scan equipment; optimizes inspection recipes; and applies statistical process control to detect tool or process deviations early.

The role partners with module and integration teams, including Etch, Thin Film, Lithography, and Diffusion, and provides technical support to customers. Additional work includes transferring products and technologies from TSMC headquarters, reviewing WAT and online/offline abnormal signals, implementing containment and preventative actions, improving yield and wafer acceptance test stability, reducing process defects, and developing customized structure process integration.

This position is fully on-site at the TSMC Washington campus in Camas, Washington. Standard hours are Monday through Friday, 8:00 AM–5:00 PM, with additional hours as needed for business and project milestones. Production sustaining engineers may need to work condensed 12-hour rotating shifts or participate in on-duty weekend rotations. The starting salary range for new hires is $87,000–$106,764 per year; the full position range is $87,000–$115,580 per year. Sign-on bonus and relocation assistance may be available subject to qualifications and eligibility.

Requirements

• Bachelor’s, master’s, or Ph.D. in Materials Science, Electrical Engineering, Chemical Engineering, Physics, or a related STEM field.
• Comprehensive understanding of semiconductor physics, CMOS fabrication flows, failure analysis methodologies, and advanced statistical modeling software.
• Strong communication skills and ability to work as a team player.
• Detail-oriented, with strong troubleshooting and problem-solving skills.
• Project management capability.
• Familiarity with SPC concepts and practice and statistical data analysis.
• Self-starting and highly motivated.
• 0–2 years of related experience.
• Ability to convey complex technical concepts.
• Able to maintain focus and accuracy on intricate tasks while managing deadlines and pressure.
• Flexibility to work additional hours as needed; production sustaining work may involve 12-hour rotating shifts or on-duty weekend rotations.

Nice To Haves

• Programming experience.
• Semiconductor fabrication experience.

Responsibilities

• Use physical failure analysis, statistical data monitoring, and electrical characterization to identify complex tool- or loop-level defect modes.
• Set defect-reduction goals and optimize manufacturing steps with integration and module teams.
• Lead continuous-improvement tasks for baseline yield expansion and defect-density reduction.
• Own inline defect inspection, review, and scan equipment, including optical systems.
• Program, tune, and advance inline inspection recipes to improve detection sensitivity while minimizing false counts.
• Apply statistical process control algorithms to identify tool or process deviations early.
• Collaborate with Etch, Thin Film, Lithography, and Diffusion module engineers to isolate tool-induced particle or defect signatures.
• Translate inline defect and yield metrics into actionable engineering data to support customer product run-rates and address manufacturing concerns.
• Transfer new products and technologies from TSMC headquarters.
• Review daily WAT and online/offline abnormal signals and implement containment and preventative actions.
• Collaborate with FAB engineering teams to improve yield and WAY stability and reduce process defects.
• Provide technical support to mixed-signal customers.
• Develop customized structure process integration.

Benefits

• Sign-on bonus, subject to candidate qualifications and eligibility.
• Relocation assistance, subject to candidate qualifications and eligibility.
• Performance-based profit sharing.
• Incentive bonuses.
• Tuition assistance.
• Medical insurance.
• Dental insurance.
• Vision insurance.
• Employee wellness program.
• Basic life insurance and accidental death and dismemberment coverage.
• 401(k) retirement plan with company match.
• Employee Stock Purchase Program.
• 12 paid holidays per year.
• 120 hours of accrued paid time off during the first year.
• On-site fitness center, game room, physical therapist, and subsidized café.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level