Yield Enhancement Engineer

TSMC•Camas, WA

1d•$87,000 - $115,580•Onsite

About The Position

TSMC Washington is seeking a Yield Enhancement Engineer for its on-site campus in Camas, Washington. The role connects process data to customer satisfaction by identifying, analyzing, and eliminating physical or electrical defect sources that limit wafer yields. Working in a high-volume manufacturing cleanroom environment, the engineer uses metrology, data analytics, and cross-functional collaboration to prevent production excursions and optimize mature CMOS process nodes. The engineer owns inline defect inspection, review, and scan equipment; develops and optimizes inspection recipes; applies statistical process control to detect process or tool deviations; and works with module and integration teams on defect reduction and yield improvement. The position also supports customer products, technology transfers, daily signal review, yield stability, and customized process integration development. The position is fully on-site in Camas, Washington. Standard hours are Monday through Friday, 8:00 AM–5:00 PM, with additional hours as needed. Production-sustaining engineers may need to adapt to a condensed 12-hour rotating shift or participate in weekend on-duty rotations.

Requirements

Bachelor’s, Master’s, or Ph.D. in Materials Science, Electrical Engineering, Chemical Engineering, Physics, or a related STEM field.
Comprehensive understanding of semiconductor physics, CMOS fabrication flows, failure analysis methodologies, and advanced statistical modeling software.
Strong communication skills and ability to work as a team player.
Detail-oriented, with excellent troubleshooting and problem-solving skills.
Project management capability.
Familiarity with SPC concepts, practice, and statistical data analysis.
Self-starting and highly motivated.
0–2 years of related experience.

Nice To Haves

Programming experience.
Semiconductor fabrication experience.

Responsibilities

Use physical failure analysis, statistical data monitoring, and electrical characterization to identify tool- or loop-level defect modes.
Establish defect-reduction goals and optimize manufacturing steps with integration and module teams.
Lead continuous-improvement work to expand baseline yield and reduce baseline defect density.
Serve as technical owner of inline defect inspection, review, and scan equipment, including optical systems.
Program, tune, and advance inline inspection recipes to improve defect-detection sensitivity while minimizing false counts.
Use statistical process control algorithms to identify tool or process deviations early.
Collaborate with Etch, Thin Film, Lithography, and Diffusion engineers to isolate tool-induced particle or defect signatures.
Translate inline defect and yield metrics into actionable engineering data to support customer product run-rates and address manufacturing concerns.
Transfer new products and technologies from TSMC headquarters.
Review daily WAT and online/offline abnormal signals, and implement containment and preventive actions.
Collaborate with the FAB engineering team to improve yield and WAY stability and reduce process defects.
Provide technical support to mixed-signal customers.
Develop customized structure process integration.

Benefits

Sign-on bonus, subject to candidate qualifications and eligibility.
Relocation assistance, subject to candidate qualifications and eligibility.
Performance-based profit sharing.
Incentive bonuses.
Tuition assistance.
Comprehensive medical insurance.
Dental insurance.
Vision insurance.
Employee wellness program.
Basic life insurance and accidental death and dismemberment coverage.
401(k) retirement plan with company match.
Employee Stock Purchase Program.
12 paid holidays per year.
120 hours of accrued paid time off during the first year.
On-site fitness center, interactive game room, on-site physical therapist, and subsidized café.