About The Position

The Wireless MAC Design Verification Engineer will contribute to verification initiatives within Apple’s Wireless Connectivity Silicon (WCS) group, helping ensure products incorporate cutting-edge Wi-Fi technology while maintaining quality and reliability. The role involves work across the ASIC design verification cycle, with opportunities to deepen knowledge of Wi-Fi protocols, complex IP and subsystems, and fabric protocols. The engineer will collaborate with system architects and design, software, and firmware teams. Responsibilities include detailed test planning, adapting to evolving requirements, building testbench infrastructure, running regressions, closing coverage, and using AI tools to streamline verification processes and expedite debugging. The WCS team develops wireless connectivity SoCs, including the N1 family, for current and future Apple products.

Requirements

  • Bachelor of Science degree.
  • At least 10 years of relevant industry experience.
  • Advanced knowledge of standard ASIC design and verification flows.
  • Proven track record leading verification methodology for clusters, subsystems, or full-chip-level designs.
  • Deep proficiency in object-oriented programming (OOP), SystemVerilog, and UVM.
  • Strong analytical and problem-solving skills, including the ability to debug complex design issues effectively.

Nice To Haves

  • Knowledge of wireless connectivity or MAC verification.
  • Experience using AI-based tools for verification, such as Claude Code or similar, to improve efficiency and automation.
  • Motivation, ambition, and ability to collaborate effectively in a dynamic, fast-paced work environment.

Responsibilities

  • Contribute to verification initiatives for wireless connectivity products.
  • Develop detailed test plans and adapt them as requirements evolve.
  • Build testbench infrastructure.
  • Perform regressions and close coverage.
  • Use AI tools to streamline design verification processes and expedite debugging.
  • Collaborate with system architects and design, software, and firmware teams.
  • Lead verification methodology for clusters, subsystems, or full-chip-level designs.
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