Wafer Sort Test Engineer

Samsung•Austin, TX

2d•Onsite

About The Position

Samsung is a world leader in advanced semiconductor technology, founded on the belief that the pursuit of excellence creates a better world. At SAS, we are Innovating Today to Power the Devices of Tomorrow. Come innovate with us! Position Summary In your role as a Test Engineer at Samsung, you will directly impact upcoming process technologies by providing feedback for Logic & SRAM test vehicles to process architecture teams. Additionally, you can expand your experience by evaluating process BKMs on various high volume manufacturing products that defines Samsung's competitive edge.

Requirements

B.S / M.S in Electrical Engineering or equivalent experience
10+ years of Test Engineering with Advantest V93K and/or UltraFLEX test platforms.
Wafer Sort test programs will range from LOGIC / SRAM test vehicles to complex full product testing at wafer sort (SoC, RF, Memory, etc applications).
Prior experience in designing, developing, and deploying scalable test infrastructure (hardware and software) in high-volume manufacturing (HVM) environment.
Familiarity with TEL prober and driver communication.
Coding & scripting experience needed for debug purposes
Demonstrated ability to serve as a technical lead, mentor junior engineers, and drive cross-functional alignment between Design, Product, Test, and Manufacturing teams.
Excellent written and verbal communication skills.

Responsibilities

Implementing testing solutions for Multi Product Wafer (MPW) Test Vehicles and upcoming new products for Samsung's latest process technology.
Driving Innovation in Test Engineering within a high-volume production testing on the Advantest V93000 and/or UltraFLEX test platforms to provide technical execution in developing robust, scalable, and optimized test infrastructure.
Designing / verifying hardware, including probe cards and interface boards to support New Product / Technology Introduction and accelerate time to market for our end customers; ensuring tester licensing and hardware resources to fit product needs.
Adding/Updating Test patterns, verify across process, voltage, and temperature.
Implement Vmin/Vmax data collection for various products.
Implementing wafer level SCAN diagnostics and SRAM Bitmap data, post process and analysis.
Debugging tool / probing card issues, managing test program revisions, updating prober interface that interact with internal systems.