Senior/Lead VLS Engineer - Global Circuits
About The Position
SambaNova is seeking a Senior / Lead VLSI Design Engineer to architect and own global circuit areas, including custom clocking, low-power design techniques, and power distribution integrity. The role involves designing and optimizing ultra-low-jitter, low-skew, low-power custom clock distribution networks, performing power analysis, and applying expertise in PLL, ESD, Latch-Up, and IO design to ensure seamless SoC integration and compliance with performance and reliability targets. The engineer will collaborate with Physical Design teams and specialized IP teams, and drive pre-silicon reliability and clock-timing sign-off before tape-out. The role also supports post-silicon bring-up and requires cross-functional work to integrate chip-level solutions.
Requirements
- Bachelor’s or Master’s degree in Electrical Engineering or Microelectronics.
- At least 8 years of custom analog/mixed-signal VLSI design experience in advanced process nodes, such as FinFET or GAA at 7nm, 5nm, 3nm, or 2nm.
- Experience designing custom clock networks, low-power design techniques, and custom IO/ESD/Latch-Up circuits.
- Knowledge of physical layout requirements for high-speed clocking, parasitic extraction, and low-resistance interconnects.
- Strong cross-functional collaboration and technical communication skills to bridge chip architecture and specialized IP deliverables.
- Experience with transistor-level circuit simulators, Transmission Line Theory, jitter and skew analysis/methodology, PERC, ESD, EM/IR analysis, and parasitic extraction tools.
- Familiarity with leading semiconductor foundry ESD and Latch-Up design rules, guard-ring guidelines, and sign-off flows across advanced nodes.
Nice To Haves
- MS or Ph.D. in Electrical Engineering with experience in custom Analog/Mixed-Signal IC Design or silicon reliability.
- At least 10 years of industry experience and a track record of driving complex top-level silicon integrations.
- Experience using modern AI tools and AI-assisted workflows to write scripts such as Python, TCL, or SKILL for flow automation, productivity enhancement, and simulation post-processing.
Responsibilities
- Architect, design, and optimize transistor-level custom chip-level clock distribution networks, including H-trees, grids, meshes, and hybrid topologies.
- Perform signal-integrity, power-integrity, jitter, skew, and EM/IR analyses across chip-level clock distribution networks.
- Contribute to low-power design methodology and perform power analysis of key components.
- Perform power distribution integrity analysis.
- Collaborate with Physical Design teams on floor planning, custom routing, shielding strategies, and Clock Tree Synthesis (CTS) guidelines.
- Partner with IP teams to select, evaluate, and integrate custom IO pads, level translators, ESD clamps, and rail protection structures according to ESD/Latch-Up methodology.
- Drive pre-silicon chip-level reliability and clock-timing sign-off before tape-out, and support post-silicon bring-up.
Benefits
- Equity and benefits as part of a competitive total rewards package.
- 95% premium coverage for employee medical insurance and 77% premium coverage for dependent medical insurance.
- Health Savings Account (HSA) with employer contribution.
- Dental, vision, short- and long-term disability, basic life, voluntary life, and AD&D insurance plans.
- Flexible Spending Account (FSA) options for health care, limited purpose, and dependent care.
- Headspace subscription, Gympass+ membership, One Medical membership, counseling services through an Employee Assistance Program, and other well-being benefits.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
