Senior/Lead VLS Engineer - Global Circuits

SambaNova Systems • San Jose, CA

2d

About The Position

SambaNova is seeking a Senior / Lead VLSI Design Engineer to architect and own global circuit areas, including custom clocking, low-power design techniques, and power distribution integrity, while championing chip-level PLL, IO, ESD, and Latch-Up strategy and integration. The role involves designing and optimizing ultra-low-jitter, low-skew, low-power custom clock distribution networks and performing in-depth power analysis and developing low-power solutions. The engineer will partner with specialized IP teams to support seamless SoC integration and chip-level compliance with performance and reliability targets.

The team integrates SambaNova AI accelerators into rack-scale systems for deployment in customer datacenters, supporting prototype and production environments and taking rack solutions from prototyping through mass production. The role collaborates across engineering and other functions and supports pre-silicon reliability and clock-timing sign-off before tape-out, as well as post-silicon bring-up.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering or Microelectronics.
• At least 8 years of custom analog/mixed-signal VLSI design experience in advanced process nodes such as FinFET or GAA (for example, 7nm, 5nm, 3nm, or 2nm).
• Experience designing custom clock networks, low-power design techniques, and custom IO/ESD/Latch-Up circuits.
• Deep knowledge of physical layout requirements for high-speed clocking, parasitic extraction, and low-resistance interconnects.
• Strong cross-functional collaboration and technical communication skills to bridge chip architecture with specialized IP deliverables.
• Experience with transistor-level circuit simulators, Transmission Line Theory, jitter and skew analysis/methodology, PERC, ESD, EM/IR analysis, and parasitic extraction tools.
• Deep familiarity with leading semiconductor foundry ESD and Latch-Up design rules, guard-ring guidelines, and sign-off flows across advanced nodes.

Nice To Haves

• MS or Ph.D. in Electrical Engineering with experience in custom Analog/Mixed-Signal IC Design or silicon reliability.
• At least 10 years of industry experience and a track record of driving complex top-level silicon integrations.
• Experience using modern AI tools and AI-assisted workflows to write scripts, such as Python, TCL, or SKILL, for flow automation, productivity enhancement, and simulation post-processing.

Responsibilities

• Architect, design, and optimize transistor-level custom chip-level clock distribution networks, including H-trees, grids, meshes, or hybrid topologies.
• Perform signal integrity, power integrity, jitter, skew, and EM/IR analyses across chip-level clock distribution networks.
• Contribute to low-power design methodology and perform power analysis of key components.
• Perform power distribution integrity analysis.
• Collaborate with Physical Design teams on floor-planning, custom routing, shielding strategies, and Clock Tree Synthesis (CTS) guidelines.
• Partner with IP teams to select, evaluate, and integrate custom IO pads, level translators, primary and secondary ESD clamps, and rail protection structures specified by ESD/Latch-Up methodology.
• Drive pre-silicon chip-level reliability and clock-timing sign-off before tape-out, and support post-silicon bring-up.

Benefits

• Equity
• Employee medical insurance with 95% premium coverage
• Dependent medical insurance with 77% premium coverage
• Health Savings Account (HSA) with employer contribution
• Dental insurance
• Vision insurance
• Short- and long-term disability insurance
• Basic and voluntary life insurance
• AD&D insurance
• Flexible Spending Account (FSA) options for health care, limited purpose, and dependent care
• Headspace subscription
• Gympass+ membership with access to physical gyms
• One Medical membership
• Counseling services through an Employee Assistance Program

What This Job Offers

• Job Type: Full-time
• Career Level: Senior