TPU Compute RTL Design Engineer
About The Position
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As an ASIC Design Engineer, you will be part of a team developing ASICs used to accelerate computation in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 8 years of experience with digital design using SystemVerilog RTL.
- Experience with power, performance and area optimizations.
Nice To Haves
- Experience interacting with software, architecture, physical design and other cross-functional teams.
- Knowledge of processor design, accelerators, or memory hierarchies.
Responsibilities
- Work independently to create and review the compute subsystem's design microarchitecture specifications.
- Define compute subsystem integration requirements to the SOC.
- Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
- Work with design validation (DV) teams to create testplans to verify, and debug design RTL.
- Work with physical design teams to ensure design meets physical requirements and timing closure.
Benefits
- 15% bonus target
- equity
- benefits
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What This Job Offers
Job Type
Full-time
Career Level
Senior
