Senior Staff RTL Design Engineer

Marvell TechnologyBoise, ID
$135,900 - $201,130

About The Position

The Senior Staff SoC Design Engineer role focuses on SoC microarchitecture, RTL design, and full-chip integration for high-performance designs. The position involves implementing and integrating complex IP across subsystems, ensuring correct functionality while meeting performance, power, and area (PPA) targets at the SoC level. Responsibilities span the full front-end design flow — from architecture and specification through RTL development, integration, and design sign-off — in close collaboration with verification, physical design, and architecture teams.

Requirements

  • Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 8-12 years of related professional experience.
  • Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience.
  • Experience in Micro-architecture for complex Custom SoC/ASIC products.
  • Excellent Logic design and debug skills.
  • RTL design experience, Synthesis, static-timing closure, formal verification, gate-level simulations and block-level function verification.
  • Hands-on experience for all aspects of chip-development process with proficiency in front-end design tools and methodologies is a must.
  • Experience with highspeed, low power, and area optimized designs.
  • Experience working with multi-clock designs, DFT, resets, LEC, Lint, etc.

Nice To Haves

  • Design knowledge of one/more industry-standard bus protocols (AXI, AHB, APB) a plus.
  • Knowledge of scripting languages, such as Python

Responsibilities

  • Define microarchitecture and develop Verilog/SystemVerilog RTL for SoC-level components, including interconnects, memory interfaces, and global logic such as reset, clocking, and power management.
  • Collaborate with verification teams to review test plans, support functional debug, and help close coverage gaps during development.
  • Run standard design checks such as lint and CDC/RDC, define timing constraints, and work with synthesis and physical design teams to ensure the design meets implementation requirements.
  • Coordinate with IP teams to integrate complex interfaces and resolve subsystem-level issues.
  • Contribute to design methodology, improve integration workflows, and provide technical guidance to other engineers.

Benefits

  • employee stock purchase plan with a 2-year look back
  • family support programs to help balance work and home life
  • robust mental health resources to prioritize emotional well-being
  • recognition and service awards to celebrate contributions and milestones
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