Third-Party SerDes PHY Technical Lead

Advanced Micro Devices, Inc•Austin, TX

11d

About The Position

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. THE ROLE: The candidate will join a highly visible and influential team of high-speed physical interface (PHY) and mixed-signal IP specialists responsible for the integration and support of third-party SERDES interfaces across AMD products. The team collaborates with AMD integration, validation, and post-silicon teams, as well as external IP vendors and customers. THE PERSON: The ideal candidate has expertise in third-party SERDES IP integration and support, including interfaces such as PCIe, USB, DisplayPort/HDMI, MIPI C-PHY and M-PHY, Ethernet, and UCIe. The candidate should be able to contribute both independently and collaboratively while working with cross-functional engineering teams, external partners, and vendors.

Requirements

Expertise in third-party SERDES IP integration and support, including interfaces such as PCIe, USB, DisplayPort/HDMI, MIPI C-PHY and M-PHY, Ethernet, and UCIe.
Ability to contribute both independently and collaboratively while working with cross-functional engineering teams, external partners, and vendors.
Experience in semiconductor engineering with a focus on analog/mixed-signal circuit or system design, analysis, validation, testing, characterization, or debug.
Knowledge of high-speed I/O SERDES architectures and related circuit blocks, such as CTLE, FFE, DFE, VGA, CDR, PLL/DLL, TX drivers, EMC, GPIO, and other mixed-signal IP components.
Experience with one or more interface protocols, including PCIe, Ethernet, USB, DisplayPort, HDMI, MIPI, UCIe, or similar technologies.
Familiarity with advanced FinFET semiconductor process technologies.
Understanding of RTL design, logic design, and digital circuits.
Experience with scripting or automation using Python, Perl, or similar languages, and familiarity with UNIX or Linux environments.
Experience using AI-assisted tools to enhance engineering workflows and productivity.
Laboratory experience using equipment such as BERTs, oscilloscopes, logic analyzers, or similar tools to perform electrical or functional validation.
Demonstrated analytical and problem-solving capabilities with attention to technical detail.
Ability to communicate technical concepts effectively through written and verbal communication and collaboration with cross-functional teams.
Bachelor's or master’s degree in electrical engineering or a related engineering discipline preferred.

Responsibilities

Serve as the AMD technical owner for various third-party SERDES IPs, providing pre-silicon and post-silicon technical leadership and support.
Work directly with third-party IP vendors to support design transfer, release of design views and collateral, and integration of IP across AMD products.
Partner with AMD integration teams to ensure electrical, logical, and physical quality throughout the integration process.
Support IC package and PCB design teams in completing and evaluating signal integrity and power integrity analyses.
Perform technical evaluations of new IP for potential licensing.
Provide post-silicon support including first silicon bring-up, debug, ATE production testing, lab validation, characterization, compliance testing, and customer support activities.
Contribute to continuous improvement by leveraging post-silicon learnings to provide feedback and recommendations for future SERDES IP designs.