Technical Lead Digital Design Engineer

Astera Labs • San Jose, CA

2d • $160,000 - $200,000

About The Position

Astera Labs is hiring a Technical Lead Digital Design Engineer to contribute to the design and implementation of next-generation digital designs for high-performance connectivity solutions. The role works on complex design blocks from micro-architecture through silicon bring-up, collaborating with verification, physical design (PD), and design-for-test (DFT) teams to deliver high-performance products in a fast-paced, collaborative environment.

The engineer owns RTL implementation from micro-architecture through sign-off, supports verification, timing closure, and DFT efforts, and develops scripting and automation to improve ASIC methodology. The role is accountable for design quality and overall success with support from senior engineers.

Requirements

• Bachelor’s degree in electrical engineering or equivalent.
• At least 5 years of experience developing SoC or silicon products in the server, storage, and/or networking markets.
• Expertise in RTL coding with SystemVerilog and synthesis using Synopsys or Cadence.
• Track record of delivering high-quality digital designs from definition to production.
• Experience with high-speed design in advanced technology nodes.
• Understanding of functional and formal verification at block and chip level.
• Understanding of clocking, CDC, RDC, and static-timing analysis.
• Proficiency with high-speed protocols such as PCIe, Ethernet, DDR, or similar.
• Experience with IP development and integration.
• Expertise in design methodology, CAD automation, or design infrastructure.
• Proven SystemVerilog and Python expertise in a production environment.
• Familiarity with Synopsys and/or Cadence digital design flows.
• Basic understanding of UVM-based verification methodologies.
• Eagerness to learn and grow, with the ability to balance multiple priorities in a dynamic environment.
• Good communication and collaboration skills, including comfort working cross-functionally with global teams.
• Ability to learn independently and adapt quickly to changing requirements.
• Customer-focused mindset and ability to prioritize and work independently to deliver high-quality designs.

Nice To Haves

• Experience with embedded firmware development or standard embedded processor subsystems such as RISC-V or Arm.
• Knowledge of DFT in a production environment.

Responsibilities

• Own RTL implementation of complex digital designs from micro-architecture through sign-off.
• Collaborate with verification teams to review test plans and debug issues.
• Support timing closure and implementation of Design-for-Test (DFT) features.
• Develop scripting and automation to improve ASIC methodology.
• Be accountable for design quality and overall design success, with support from senior engineers.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior