Technical Lead Digital Design Engineer

Astera Labs • San Jose, CA

1d

About The Position

Join Astera Labs as a Technical Lead Digital Design Engineer, contributing to the design and implementation of next-generation digital designs for high-performance connectivity solutions. The role involves working on complex blocks from micro-architecture through silicon bring-up and collaborating with verification, physical design (PD), and Design-for-Test (DFT) teams to deliver high-performance products in a fast-paced, collaborative environment.

The position owns RTL implementation of complex digital designs through sign-off and supports design quality and overall success with senior engineers. It also contributes to timing closure, DFT implementation, and scripting and automation to improve ASIC methodologies.

Requirements

• Bachelor’s degree in electrical engineering or equivalent.
• At least 5 years of experience developing SoC or silicon products in Server, Storage, and/or Networking markets.
• Expertise in RTL coding with SystemVerilog and synthesis using Synopsys or Cadence.
• Track record of delivering high-quality digital designs from definition to production.
• Experience with high-speed design in advanced technology nodes.
• Understanding of functional and formal verification at block and chip level.
• Understanding of clocking, CDC, RDC, and static-timing analysis.
• Proficiency with high-speed protocols such as PCIe, Ethernet, DDR, or similar.
• Experience with IP development and integration.
• Expertise in design methodology, CAD automation, or design infrastructure.
• Production-environment expertise with SystemVerilog and Python.
• Familiarity with Synopsys and/or Cadence digital design flows.
• Basic understanding of UVM-based verification methodologies.
• Strong eagerness to learn and grow, with the ability to balance multiple priorities in a dynamic environment.
• Good communication and collaboration skills, including comfort working cross-functionally with global teams.
• Ability to learn independently and adapt quickly to changing requirements.
• Customer-focused mindset and ability to prioritize and work independently to deliver high-quality designs.

Nice To Haves

• Experience with embedded firmware development or standard embedded processor subsystems such as RISC-V or Arm.
• Knowledge of Design-for-Test (DFT) in a production environment.

Responsibilities

• Own RTL implementation of complex digital designs from micro-architecture through sign-off.
• Collaborate with verification teams to review test plans and debug issues.
• Support efforts to achieve timing closure and implement Design-for-Test (DFT) features.
• Develop scripting and automation to improve ASIC methodology.
• Contribute to design quality and overall design success with support from senior engineers.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior