Tech Lead FPGA /Senior Design Verification Engineer (SystemVerilog / UVM)

American IT Systems • Seattle, WA

1d • Onsite

About The Position

We are seeking a Tech Lead FPGA / Senior Design Verification Engineer with expertise in SystemVerilog and UVM. The role involves leading a design verification team and contributing to IP verification from scratch. This is a long-term, onsite position at a customer location in Redmond, Seattle, Washington.

Requirements

• Minimum 8 years of total design verification experience.
• Experience in IP verification using UVM methodology from scratch.
• Knowledge of AMBA Protocol.
• Experience in VIP integration to your Testbench Environment.
• Led a design verification team.
• Design Verification expertise in SystemVerilog / UVM for Unit/Module level Verification.
• Strong background in developing UVM Testbenches from scratch.
• Experience in VIP Integration and Bring up.
• Porting Existing Verilog/VHDL environment to UVM based Environment.
• Experience in test planning, Coverage Coding and Debugging.
• Deep Knowledge of AMBA Protocol is a must.

Responsibilities

• Lead a design verification team of at least 5 members.
• Develop UVM Testbenches from scratch.
• Perform IP verification using UVM methodology.
• Integrate VIP into the Testbench Environment.
• Port existing Verilog/VHDL environments to UVM-based environments.
• Engage in test planning, coverage coding, and debugging.
• Ensure deep knowledge and application of AMBA Protocol.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed